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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td19 // Core - 32-bit core registers
31 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
35 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
39 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
44 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;
46 def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>;
47 def FP : Core<27, "%fp", ["%r27"]>, DwarfRegNum<[27]>;
49 def ILINK : Core<29, "%ilink">, DwarfRegNum<[29]>;
50 def R30 : Core<30, "%r30">, DwarfRegNum<[30]>;
51 def BLINK : Core<31, "%blink">, DwarfRegNum<[31]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonShuffler.cpp233 unsigned Units = ISJ.Core.getUnits(); in restrictNoSlot1Store()
238 ISJ.Core.setUnits(Units & ~Slot1Mask); in restrictNoSlot1Store()
315 ISJ.Core.setAllUnits(); in permitNonSlot()
368 if (!ISJ->Core.getUnits()) in restrictStoreLoadOrder()
387 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad); in restrictStoreLoadOrder()
399 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); in restrictStoreLoadOrder()
419 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore); in restrictStoreLoadOrder()
427 ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); in restrictStoreLoadOrder()
589 return (I.Core.getUnits() == Slot3Mask); in restrictPreferSlot3()
607 PrefSlot3Inst->Core.setUnits(saveUnits); in restrictPreferSlot3()
[all …]
H A DHexagonShuffler.h103 HexagonResource Core; variable
110 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
117 return (HexagonResource::lessWeight(B.Core, Core));
122 return (HexagonResource::lessUnits(A.Core, B.Core)); in lessCore()
/freebsd/lib/clang/liblldb/
H A DMakefile157 SRCS+= Core/Address.cpp
163 SRCS+= Core/Debugger.cpp
175 SRCS+= Core/IOHandler.cpp
177 SRCS+= Core/Mangled.cpp
178 SRCS+= Core/Module.cpp
180 SRCS+= Core/ModuleList.cpp
181 SRCS+= Core/Opcode.cpp
183 SRCS+= Core/Progress.cpp
186 SRCS+= Core/Section.cpp
192 SRCS+= Core/Value.cpp
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mips/loongson/
H A Ddevices.yaml20 - description: Classic Loongson64 Quad Core + LS7A
24 - description: Classic Loongson64 Quad Core + RS780E
28 - description: Classic Loongson64 Octa Core + RS780E
32 - description: Generic Loongson64 Quad Core + LS7A
36 - description: Virtual Loongson64 Quad Core + VirtIO
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DOpenCLOptions.h95 unsigned Core = 0U; member
109 : WithPragma(Pragma), Avail(AvailV), Core(CoreV), Opt(OptV) {} in OpenCLOptionInfo()
111 bool isCore() const { return Core != 0U; } in isCore()
123 return isAvailableIn(LO) && isOpenCLVersionContainedInMask(LO, Core); in isCoreIn()
/freebsd/contrib/file/magic/Magdir/
H A Ddigital28 # The actual magic number is just "Core", followed by a 2-byte version
29 # number; however, treating any file that begins with "Core" as a Digital
34 0 string Core\001 Alpha COFF format core dump (Digital UNIX)
36 0 string Core\002 Alpha COFF format core dump (Digital UNIX)
/freebsd/lib/clang/libclang/
H A DMakefile737 SRCS_FUL+= StaticAnalyzer/Core/APSIntType.cpp
742 SRCS_FUL+= StaticAnalyzer/Core/BugReporter.cpp
746 SRCS_FUL+= StaticAnalyzer/Core/CallEvent.cpp
747 SRCS_FUL+= StaticAnalyzer/Core/Checker.cpp
754 SRCS_FUL+= StaticAnalyzer/Core/CoreEngine.cpp
759 SRCS_FUL+= StaticAnalyzer/Core/ExprEngine.cpp
768 SRCS_FUL+= StaticAnalyzer/Core/MemRegion.cpp
776 SRCS_FUL+= StaticAnalyzer/Core/SVals.cpp
780 SRCS_FUL+= StaticAnalyzer/Core/Store.cpp
783 SRCS_FUL+= StaticAnalyzer/Core/WorkList.cpp
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,apr-services.yaml22 3 = DSP Core Service
29 10 = Core voice stream.
30 11 = Core voice processor.
H A Dqcom,apr.txt36 3 - DSP Core Service
43 10 - Core voice stream.
44 11 - Core voice processor.
/freebsd/contrib/llvm-project/clang/include/
H A Dmodule.modulemap147 module Clang_Rewrite { requires cplusplus umbrella "clang/Rewrite/Core" module * { export * } }
162 umbrella "clang/StaticAnalyzer/Core"
164 textual header "clang/StaticAnalyzer/Core/Analyses.def"
165 textual header "clang/StaticAnalyzer/Core/AnalyzerOptions.def"
166 textual header "clang/StaticAnalyzer/Core/PathSensitive/SVals.def"
167 textual header "clang/StaticAnalyzer/Core/PathSensitive/Symbols.def"
168 textual header "clang/StaticAnalyzer/Core/PathSensitive/Regions.def"
202 umbrella "clang/Tooling/Core" module * { export * }
/freebsd/sys/contrib/device-tree/Bindings/arm/stm32/
H A Dstm32.yaml116 - description: Engicam i.Core STM32MP1 SoM based Boards
119 - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
120 … - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
121 … - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
122 - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
/freebsd/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,omap-dss.txt11 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
15 The DSS Core is the parent of the other DSS modules, and manages clock routing,
27 The DSS Core and the encoders have video port outputs. The structure of the
90 DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-corediv-clock.txt1 * Core Divider Clock bindings for Marvell MVEBU SoCs
12 - reg : must be the register address of Core Divider control register
H A Ddove-divider-clock.txt18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
/freebsd/sys/contrib/device-tree/Bindings/soc/nuvoton/
H A Dnuvoton,gfxi.yaml7 title: Graphics Core Information block in Nuvoton SoCs
14 The Graphics Core Information (GFXI) are a block of registers in Nuvoton SoCs
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dgmu.yaml97 - description: Core GMU registers
129 - description: Core GMU registers
166 - description: Core GMU registers
185 - description: Core GMU registers
231 - description: Core GMU registers
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dimg-ir-rev1.txt16 1st: Core clock (defaults to 32.768KHz if omitted).
22 "core": Core clock.
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV67T.td1 //=- HexagonScheduleV67T.td - Hexagon V67 Tiny Core Scheduling Definitions --=//
60 // Hexagon V67 Tiny Core Resource Definitions -
H A DHexagonScheduleV71T.td1 //=-HexagonScheduleV71T.td - Hexagon V71 Tiny Core Scheduling Definition ----=//
58 // Hexagon V71 Tiny Core Resource Definitions -
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt8103-pmgr.dtsi16 apple,always-on; /* Core device */
25 apple,always-on; /* Core device */
34 apple,always-on; /* Core device */
75 apple,always-on; /* Core device */
84 apple,always-on; /* Core device */
138 apple,always-on; /* Core device */
1015 apple,always-on; /* Core AON device */
1024 apple,always-on; /* Core AON device */
1033 apple,always-on; /* Core AON device */
1042 apple,always-on; /* Core AON device */
[all …]
/freebsd/contrib/llvm-project/lldb/source/Utility/
H A DArchSpec.cpp25 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
36 ArchSpec::Core core;
253 ArchSpec::Core core;
1082 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2, in cores_match()
1399 const ArchSpec::Core lhs_core = lhs.GetCore(); in operator <()
1400 const ArchSpec::Core rhs_core = rhs.GetCore(); in operator <()
1453 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m || in IsAlwaysThumbInstructions()
1455 GetCore() == ArchSpec::Core::eCore_arm_armv6m || in IsAlwaysThumbInstructions()
1456 GetCore() == ArchSpec::Core::eCore_thumbv7m || in IsAlwaysThumbInstructions()
1457 GetCore() == ArchSpec::Core::eCore_thumbv7em || in IsAlwaysThumbInstructions()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dactions.yaml28 - const: caninos,labrador-v2 # Labrador Core v2
40 - const: caninos,labrador-v3 # Labrador Core v3
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Dstarfive,jh7100-wdt.yaml40 - description: Core clock
50 - description: Core reset
/freebsd/contrib/llvm-project/lldb/include/lldb/Utility/
H A DArchSpec.h116 enum Core { enum
429 Core GetCore() const { return m_core; } in GetCore()
536 Core m_core = kCore_invalid;

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