Searched refs:DepCtr (Results 1 – 10 of 10) sorted by relevance
56 namespace DepCtr {
15 namespace DepCtr { namespace
1038 namespace DepCtr {
1592 namespace DepCtr { namespace
1177 AMDGPU::DepCtr::decodeFieldVmVsrc(MI.getOperand(0).getImm()) == 0); in fixVMEMtoScalarWriteHazards()1187 .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0)); in fixVMEMtoScalarWriteHazards()1306 AMDGPU::DepCtr::decodeFieldSaSdst(MI.getOperand(0).getImm()) == 0) in fixVcmpxExecWARHazard()1317 .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0)); in fixVcmpxExecWARHazard()1469 AMDGPU::DepCtr::decodeFieldVmVsrc(I.getOperand(0).getImm()) == 0) || in fixLdsDirectVMEMHazard()1483 .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0)); in fixLdsDirectVMEMHazard()1546 AMDGPU::DepCtr::decodeFieldVaVdst(I.getOperand(0).getImm()) == 0)) in fixVALUPartialForwardingHazard()1713 .addImm(AMDGPU::DepCtr::encodeFieldVaVdst(0)); in fixVALUTransUseHazard()2819 AMDGPU::DepCtr::decodeFieldSaSdst(I.getOperand(0).getImm()) == 0) in fixVALUMaskWriteHazard()2869 .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0)); in fixVALUMaskWriteHazard()
54 AMDGPU::DepCtr::decodeFieldVaVdst(MI.getOperand(0).getImm()) == 0) in instructionWaitsForVALU()
915 def DepCtr : CustomOperand<i32>;
1691 SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtr:$simm16), "$simm16">;
7043 bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) { in parseDepCtr() argument7045 using namespace llvm::AMDGPU::DepCtr; in parseDepCtr()7077 DepCtr = (DepCtr & ~CntValMask) | CntVal; in parseDepCtr()7082 using namespace llvm::AMDGPU::DepCtr; in parseDepCtr()7084 int64_t DepCtr = getDefaultDepCtrEncoding(getSTI()); in parseDepCtr() local7090 if (!parseDepCtr(DepCtr, UsedOprMask)) in parseDepCtr()7094 if (!parseExpr(DepCtr)) in parseDepCtr()7098 Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc)); in parseDepCtr()
1654 using namespace llvm::AMDGPU::DepCtr; in printDepCtr()