Searched refs:DestSub1 (Results 1 – 3 of 3) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 7686 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local 7690 std::swap(DestSub0, DestSub1); in splitScalar64BitUnaryOp() 7696 .addReg(DestSub1) in splitScalar64BitUnaryOp() 7721 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulU64() local 7795 BuildMI(MBB, MII, DL, get(AMDGPU::V_ADD_U32_e32), DestSub1) in splitScalarSMulU64() 7802 .addReg(DestSub1) in splitScalarSMulU64() 7861 BuildMI(MBB, MII, DL, get(NewOpc), DestSub1).add(Op1L).add(Op0L); in splitScalarSMulPseudo() 7871 .addReg(DestSub1) in splitScalarSMulPseudo() 7931 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local 7932 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp() [all …]
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H A D | SILoadStoreOptimizer.cpp | 1986 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase() local 1997 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase() 2011 .addReg(DestSub1) in computeBase()
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H A D | SIISelLowering.cpp | 4767 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local 4784 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter() 4790 .addReg(DestSub1) in EmitInstrWithCustomInserter() 4823 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local 4859 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter() 4869 .addReg(DestSub1) in EmitInstrWithCustomInserter()
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