/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PostSelectOptimize.cpp | 130 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in foldSimpleCrossClassCopies() local 132 if (SrcRC == DstRC) in foldSimpleCrossClassCopies() 136 if (SrcRC->hasSubClass(DstRC)) { in foldSimpleCrossClassCopies() 146 if (!MRI.constrainRegClass(Src, DstRC, /* MinNumRegs */ 25)) in foldSimpleCrossClassCopies() 148 } else if (DstRC->hasSubClass(SrcRC)) { in foldSimpleCrossClassCopies()
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H A D | AArch64InstructionSelector.cpp | 1000 const TargetRegisterClass *DstRC; in selectCopy() local 1003 if (!DstRC) { in selectCopy() 1026 getSubRegForClass(DstRC, TRI, SubReg); in selectCopy() 3189 if (!DstRC) in select() 3202 if (DstRC == SrcRC) { in select() 3976 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues() local 4047 const TargetRegisterClass *DstRC = in emitExtractVectorElt() local 4049 if (!DstRC) { in emitExtractVectorElt() 4668 const TargetRegisterClass *DstRC = in emitVectorConcat() local 5908 const TargetRegisterClass *DstRC = in tryOptBuildVecToSubregToReg() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 206 return std::pair(SrcRC, DstRC); in getCopyRegClasses() 220 TRI.hasVectorRegisters(DstRC); in isSGPRToVGPRCopy() 285 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local 288 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence() 299 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence() 310 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence() 632 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local 635 if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) { in runOnMachineFunction() 646 if (!isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) in runOnMachineFunction() 765 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local [all …]
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H A D | AMDGPUInstructionSelector.cpp | 117 const TargetRegisterClass *DstRC in constrainCopyLikeIntrin() local 121 if (!DstRC || DstRC != SrcRC) in constrainCopyLikeIntrin() 518 const TargetRegisterClass *DstRC = in selectG_EXTRACT() local 520 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_EXTRACT() 559 if (!DstRC) in selectG_MERGE_VALUES() 620 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI)) in selectG_UNMERGE_VALUES() 824 if (!DstRC) in selectG_INSERT() 1477 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectRelocConstant() 2274 if (!SrcRC || !DstRC) in selectG_TRUNC() 2657 if (!DstRC) in selectG_CONSTANT() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
H A D | X86InstructionSelector.cpp | 290 if (SrcRC != DstRC) { in selectCopy() 316 const TargetRegisterClass *DstRC = in selectCopy() local 326 if (DstRC != SrcRC) { in selectCopy() 735 return (DstRC == &X86::FR32RegClass || DstRC == &X86::FR32XRegClass || in canTurnIntoCOPY() 736 DstRC == &X86::FR64RegClass || DstRC == &X86::FR64XRegClass) && in canTurnIntoCOPY() 780 if (!DstRC || !SrcRC) in selectTruncOrPtrToInt() 786 if (canTurnIntoCOPY(DstRC, SrcRC)) in selectTruncOrPtrToInt() 793 if (DstRC == SrcRC) { in selectTruncOrPtrToInt() 800 } else if (DstRC == &X86::GR8RegClass) { in selectTruncOrPtrToInt() 912 if (canTurnIntoCOPY(SrcRC, DstRC)) in selectAnyext() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 69 const TargetRegisterClass *DstRC, in isCrossCopy() argument 74 if (DstRC == SrcRC) in isCrossCopy() 99 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy() 102 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy() 104 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy() 105 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy() 354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local 355 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes() 447 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local 448 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
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H A D | MachineCombiner.cpp | 180 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local 181 return TRI->getMatchingSuperRegClass(SrcRC, DstRC, SrcSub) != nullptr; in isTransientMI() 189 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local 190 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI() 197 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local 198 return DstRC->contains(Src); in isTransientMI()
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H A D | PeepholeOptimizer.cpp | 520 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local 521 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY() 522 if (!DstRC) in INITIALIZE_PASS_DEPENDENCY() 628 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelect.cpp | 184 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction() local 185 if (DstRC) in runOnMachineFunction() 186 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction() 247 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local 248 if (SrcRC == DstRC) { in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 208 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local 286 if (DstRC) { in initialize() 287 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize() 290 DstRC = RC; in initialize() 484 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local 492 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns() 493 if (!DstRC) in collectPatterns() 532 DstRC)) in collectPatterns() 581 DstRC, in collectPatterns()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrMMX.td | 126 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, 127 [(set DstRC:$dst, (Int SrcRC:$src))], d>, 129 def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, 130 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>, 135 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, 137 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), 138 (ins DstRC:$src1, SrcRC:$src2), asm, 139 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>, 141 def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), 142 (ins DstRC:$src1, x86memop:$src2), asm, [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local 127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
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H A D | PPCVSXSwapRemoval.cpp | 924 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local 925 Register NewVReg = MRI->createVirtualRegister(DstRC); in handleSpecialSwappables() 938 if (DstRC == &PPC::VRRCRegClass) { in handleSpecialSwappables()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MicroMips32r6InstrInfo.td | 662 dag OutOperandList = (outs DstRC:$rs); 674 dag OutOperandList = (outs DstRC:$fs); 684 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt); 685 dag OutOperandList = (outs DstRC:$fs); 698 dag OutOperandList = (outs DstRC:$impl); 720 dag OutOperandList = (outs DstRC:$rt); 732 dag OutOperandList = (outs DstRC:$rt); 742 dag OutOperandList = (outs DstRC:$rt); 888 dag OutOperandList = (outs DstRC:$ft); 924 dag OutOperandList = (outs DstRC:$ft); [all …]
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H A D | MipsInstrFPU.td | 128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 135 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft), 162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 171 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 176 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.h | 55 unsigned SubReg, const TargetRegisterClass *DstRC,
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H A D | AVRRegisterInfo.cpp | 315 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument 321 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, in shouldCoalesce()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.h | 60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
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H A D | HexagonRegisterInfo.cpp | 355 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument 366 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 154 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local 159 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg() 163 DstRC = UseRC; in EmitCopyFromReg() 165 DstRC = SrcRC; in EmitCopyFromReg() 173 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg() 615 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local 617 Register NewVReg = MRI->createVirtualRegister(DstRC); in EmitCopyToRegClassNode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.h | 173 const TargetRegisterClass *DstRC,
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H A D | SystemZRegisterInfo.cpp | 382 const TargetRegisterClass *DstRC, in shouldCoalesce() argument 390 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64) && in shouldCoalesce()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.h | 142 unsigned SubReg, const TargetRegisterClass *DstRC,
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H A D | AArch64RegisterInfo.cpp | 1020 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument 1025 ((DstRC->getID() == AArch64::GPR64RegClassID) || in shouldCoalesce() 1026 (DstRC->getID() == AArch64::GPR64commonRegClassID)) && in shouldCoalesce() 1055 (AArch64::ZPRRegClass.hasSubClassEq(DstRC) || in shouldCoalesce()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVInstructionSelector.cpp | 868 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectCopy() local 870 assert(DstRC && in selectCopy() 876 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy() 891 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectImplicitDef() local 894 assert(DstRC && in selectImplicitDef() 897 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectImplicitDef()
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