/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 5061 unsigned ExtOp, TruncOp; in PromoteNode() local 5063 ExtOp = ISD::BITCAST; in PromoteNode() 5070 ExtOp = ISD::ANY_EXTEND; in PromoteNode() 5076 ExtOp = ISD::SIGN_EXTEND; in PromoteNode() 5080 ExtOp = ISD::ZERO_EXTEND; in PromoteNode() 5119 unsigned ExtOp, TruncOp; in PromoteNode() local 5122 ExtOp = ISD::BITCAST; in PromoteNode() 5125 ExtOp = ISD::ANY_EXTEND; in PromoteNode() 5128 ExtOp = ISD::FP_EXTEND; in PromoteNode() 5195 if (ExtOp != ISD::FP_EXTEND) in PromoteNode() [all …]
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H A D | LegalizeVectorOps.cpp | 621 unsigned ExtOp = VecVT.isFloatingPoint() ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in PromoteSETCC() local 626 Operands[0] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(0)); in PromoteSETCC() 627 Operands[1] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(1)); in PromoteSETCC()
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H A D | DAGCombiner.cpp | 17501 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local 17503 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonConstExtenders.cpp | 1535 MachineOperand ExtOp(EV); in insertInitializer() local 1546 .add(ExtOp); in insertInitializer() 1552 .add(ExtOp); in insertInitializer() 1557 .add(ExtOp) in insertInitializer() 1563 .add(ExtOp); in insertInitializer() 1571 .add(ExtOp) in insertInitializer() 1584 .add(ExtOp) in insertInitializer() 1589 .add(ExtOp); in insertInitializer()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineInternal.h | 222 Constant *getLosslessTrunc(Constant *C, Type *TruncTy, unsigned ExtOp) { in getLosslessTrunc() argument 225 ConstantFoldCastOperand(ExtOp, TruncC, C->getType(), DL); in getLosslessTrunc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrSSE.td | 5047 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))), 5056 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))), 5061 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))), 5091 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))), 5123 SDNode ExtOp> { 5125 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))), 5129 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))), 5131 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))), 5134 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))), 5136 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))), [all …]
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H A D | X86InstrAVX512.td | 10040 multiclass AVX512_pmovx_patterns_base<string OpcPrefix, SDNode ExtOp> { 10043 def : Pat<(v16i16 (ExtOp (loadv16i8 addr:$src))), 10048 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))), 10051 def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))), 10057 def : Pat<(v32i16 (ExtOp (loadv32i8 addr:$src))), 10061 def : Pat<(v16i32 (ExtOp (loadv16i8 addr:$src))), 10063 def : Pat<(v16i32 (ExtOp (loadv16i16 addr:$src))), 10066 def : Pat<(v8i64 (ExtOp (loadv8i16 addr:$src))), 10069 def : Pat<(v8i64 (ExtOp (loadv8i32 addr:$src))), 10074 multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp, [all …]
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H A D | X86ISelLowering.cpp | 18044 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local 18047 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector() 41523 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local 41527 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode() 41555 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local 41559 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode() 41610 SDValue ExtOp = TLO.DAG.getNode(Opc, DL, ExtVT, Ops); in SimplifyDemandedVectorEltsForTargetNode() local 41613 insertSubVector(UndefVec, ExtOp, 0, TLO.DAG, DL, ExtSizeInBits); in SimplifyDemandedVectorEltsForTargetNode() 55619 unsigned ExtOp = DAG.getOpcode_EXTEND_VECTOR_INREG(InOpcode); in combineEXTRACT_SUBVECTOR() local 55620 return DAG.getNode(ExtOp, DL, VT, Ext); in combineEXTRACT_SUBVECTOR()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | BasicTTIImpl.h | 2103 unsigned ExtOp = in getTypeBasedIntrinsicInstrCost() local 2108 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, RetTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost() 2170 unsigned ExtOp = IsSigned ? Instruction::SExt : Instruction::ZExt; in getTypeBasedIntrinsicInstrCost() local 2174 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, MulTy, CCH, CostKind); in getTypeBasedIntrinsicInstrCost()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstrNEON.td | 3091 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))), 3104 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn), 3723 v8i16, v8i8, OpNode, ExtOp, Commutable>; 3726 v4i32, v4i16, OpNode, ExtOp, Commutable>; 3729 v2i64, v2i32, OpNode, ExtOp, Commutable>; 3791 v8i16, v8i8, OpNode, ExtOp, Commutable>; 3794 v4i32, v4i16, OpNode, ExtOp, Commutable>; 3797 v2i64, v2i32, OpNode, ExtOp, Commutable>; 3955 IntOp, ExtOp, OpNode>; 3958 IntOp, ExtOp, OpNode>; [all …]
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H A D | ARMISelLowering.cpp | 12799 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local 12800 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineBUILD_VECTORToVPADDL()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.cpp | 505 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt() local 506 return buildInstr(ExtOp, Res, Op); in buildBoolExt()
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H A D | LegalizerHelper.cpp | 2190 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); in widenScalarAddSubOverflow() local 2192 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); in widenScalarAddSubOverflow() 2263 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in widenScalarMulo() local 2264 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); in widenScalarMulo() 2265 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); in widenScalarMulo() 7761 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in lowerSMULH_UMULH() local 7767 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); in lowerSMULH_UMULH() 7768 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); in lowerSMULH_UMULH()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | SimplifyIndVar.cpp | 1531 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local 1532 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 579 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local 580 Value *ExtRes = Builder.CreateCall(I32, { ExtOp }); in promoteUniformBitreverseToI32()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 1559 auto PromoteMULO = [&](unsigned ExtOp) { in lowerOverflowArithmetic() argument 1565 LHS = DAG.getNode(ExtOp, DL, MVT::i16, LHS); in lowerOverflowArithmetic() 1566 RHS = DAG.getNode(ExtOp, DL, MVT::i16, RHS); in lowerOverflowArithmetic()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 6341 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local 6342 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4() 14717 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local 14718 if (!ExtOp) in combineBVOfVecSExt() 14721 Index = ExtOp->getZExtValue(); in combineBVOfVecSExt()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | ValueTracking.cpp | 7908 unsigned ExtOp = CmpI->isSigned() ? Instruction::SExt : Instruction::ZExt; in lookThroughCast() local 7909 CastedTo = ConstantFoldCastOperand(ExtOp, C, SrcTy, DL); in lookThroughCast()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 7321 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op); in combineINT_TO_FP() local 7322 return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp); in combineINT_TO_FP()
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 8121 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument 8125 if (ExtOp) in packTBLDVectorList() 8126 TblOps.push_back(ExtOp); in packTBLDVectorList()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 23305 SDValue ExtOp = Src->getOperand(0); in performSignExtendInRegCombine() local 23315 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(), in performSignExtendInRegCombine() 23316 ExtOp, DAG.getValueType(ExtVT)); in performSignExtendInRegCombine()
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