| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 88 DAG_FUNCTION(minimum, 2, 0, experimental_constrained_minimum, FMINIMUM)
|
| H A D | VPIntrinsics.def | 387 VP_PROPERTY_FUNCTIONAL_SDOPC(FMINIMUM)
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 982 FMINIMUM, enumerator
|
| H A D | BasicTTIImpl.h | 1917 ISD = ISD::FMINIMUM; in getTypeBasedIntrinsicInstrCost()
|
| H A D | TargetLowering.h | 2793 case ISD::FMINIMUM: in isCommutativeBinOp()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 196 case ISD::FMINIMUM: return "fminimum"; in getOperationName()
|
| H A D | LegalizeFloatTypes.cpp | 2426 case ISD::FMINIMUM: in PromoteFloatResult()
2835 case ISD::FMINIMUM: in SoftPromoteHalfResult()
|
| H A D | LegalizeVectorOps.cpp | 389 case ISD::FMINIMUM: in LegalizeOp()
|
| H A D | LegalizeVectorTypes.cpp | 132 case ISD::FMINIMUM: in ScalarizeVectorResult()
1145 case ISD::FMINIMUM: in SplitVectorResult()
4135 case ISD::FMINIMUM: in WidenVectorResult()
|
| H A D | SelectionDAG.cpp | 473 return ISD::FMINIMUM; in getVecReduceBaseOpcode()
5198 case ISD::FMINIMUM: in isKnownNeverNaN()
6468 case ISD::FMINIMUM: in foldConstantFPMath()
12858 case ISD::FMINIMUM: in getNeutralElement()
|
| H A D | LegalizeDAG.cpp | 5258 case ISD::FMINIMUM: in PromoteNode()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | GenericOpcodes.td | 816 // FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
818 // semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.
|
| H A D | TargetSelectionDAG.td | 502 def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 610 case ISD::FMINIMUM: in fnegFoldsIntoOpcode()
4658 return ISD::FMINIMUM; in inverseMinMax()
4659 case ISD::FMINIMUM: in inverseMinMax()
4784 case ISD::FMINIMUM: in performFNegCombine()
|
| H A D | SIISelLowering.cpp | 210 ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FSQRT, ISD::FCBRT, in SITargetLowering()
853 setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, in SITargetLowering()
893 ISD::FMINIMUM, in SITargetLowering()
12400 case ISD::FMINIMUM: in isCanonicalized()
12759 case ISD::FMINIMUM: in minMaxOpcToMin3Max3Opc()
13122 case ISD::FMINIMUM: { in performExtractVectorEltCombine()
14385 case ISD::FMINIMUM: in PerformDAGCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 833 ISD::FMINIMUM, ISD::FMAXIMUM, in initActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 616 setOperationAction(ISD::FMINIMUM, MVT::f64, Legal); in SystemZTargetLowering()
621 setOperationAction(ISD::FMINIMUM, MVT::v2f64, Legal); in SystemZTargetLowering()
626 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal); in SystemZTargetLowering()
631 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal); in SystemZTargetLowering()
636 setOperationAction(ISD::FMINIMUM, MVT::f128, Legal); in SystemZTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 133 setOperationAction(ISD::FMINIMUM, T, Legal); in WebAssemblyTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 515 setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f16, Custom); in RISCVTargetLowering()
541 setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f32, Custom); in RISCVTargetLowering()
559 setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f64, Custom); in RISCVTargetLowering()
919 ISD::FMINIMUM, ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL, in RISCVTargetLowering()
949 setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, VT, Custom); in RISCVTargetLowering()
1294 ISD::IS_FPCLASS, ISD::FMAXIMUM, ISD::FMINIMUM}, in RISCVTargetLowering()
6072 case ISD::FMINIMUM: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1562 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal); in ARMTargetLowering()
1564 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal); in ARMTargetLowering()
1567 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal); in ARMTargetLowering()
1569 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal); in ARMTargetLowering()
1578 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal); in ARMTargetLowering()
1580 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal); in ARMTargetLowering()
4220 ? ISD::FMINIMUM : ISD::FMAXIMUM; in LowerINTRINSIC_WO_CHAIN()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 704 ISD::FMINIMUM, ISD::FMAXIMUM, ISD::STRICT_FADD, in AArch64TargetLowering()
771 ISD::FMINIMUM, ISD::FMAXIMUM, ISD::LROUND, in AArch64TargetLowering()
1087 ISD::FMINIMUM, ISD::FMAXIMUM, ISD::STRICT_FADD, in AArch64TargetLowering()
1464 setOperationAction(ISD::FMINIMUM, VT, Custom); in AArch64TargetLowering()
1747 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM, in addTypeForNEON()
1880 setOperationAction(ISD::FMINIMUM, VT, Custom); in addTypeForFixedLengthSVE()
6352 case ISD::FMINIMUM: in LowerOperation()
20019 return DAG.getNode(ISD::FMINIMUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 157 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote); in MipsSETargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 841 for (const auto &Op : {ISD::FMINIMUM, ISD::FMAXIMUM}) { in NVPTXTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 560 setOperationAction(ISD::FMINIMUM, VT, Action); in X86TargetLowering()
983 setOperationAction(ISD::FMINIMUM, MVT::f32, Custom); in X86TargetLowering()
1023 setOperationAction(ISD::FMINIMUM, VT, Custom); in X86TargetLowering()
1392 setOperationAction(ISD::FMINIMUM, VT, Custom); in X86TargetLowering()
1723 setOperationAction(ISD::FMINIMUM, VT, Custom); in X86TargetLowering()
2159 setOperationAction(ISD::FMINIMUM, MVT::f16, Custom); in X86TargetLowering()
28051 assert((Op.getOpcode() == ISD::FMAXIMUM || Op.getOpcode() == ISD::FMINIMUM) && in LowerFMINIMUM_FMAXIMUM()
31988 case ISD::FMINIMUM: in LowerOperation()
43917 case ISD::FMINIMUM: in scalarizeExtEltFP()
|
| H A D | X86TargetTransformInfo.cpp | 5317 : ISD::FMINIMUM; in getMinMaxReductionCost()
|