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Searched refs:FalseReg (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFoldMasks.cpp111 Register FalseReg = MI.getOperand(2).getReg(); in convertVMergeToVMv() local
114 TRI->lookThruCopyLike(FalseReg, MRI)) in convertVMergeToVMv()
H A DRISCVInstrInfo.cpp1443 MachineOperand FalseReg = MI.getOperand(Invert ? 5 : 4); in optimizeSelect() local
1445 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
1467 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp732 Register FalseReg = in convertCmovInstsToBranches() local
736 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
739 FalseReg = FRIt->second; in convertCmovInstsToBranches()
741 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
H A DX86InstrInfo.h389 Register FalseReg) const override;
H A DX86InstrInfo.cpp3996 Register FalseReg, int &CondCycles, in canInsertSelect() argument
4010 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
4034 Register FalseReg) const { in insertSelect()
4042 .addReg(FalseReg) in insertSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp504 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
506 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
530 FalseReg.setImplicit(); in optimizeSelect()
531 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1555 Register FalseReg) const { in insertSelect()
1614 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1615 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3197 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3204 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3206 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3208 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
3216 return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg; in selectReg()
3218 return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg; in selectReg()
3220 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
H A DPPCInstrInfo.h439 Register FalseReg) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp922 Register FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
923 if (FalseReg == 0) in selectSelect()
927 std::swap(TrueReg, FalseReg); in selectSelect()
966 .addReg(FalseReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp491 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
496 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
529 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
533 .addReg(FalseReg) in LowerFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp553 Register FalseReg, int &CondCycles, in canInsertSelect() argument
565 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
589 Register FalseReg) const { in insertSelect()
609 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
611 FalseReg = FReg; in insertSelect()
622 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZInstrInfo.h256 Register FalseReg) const override;
H A DSystemZISelLowering.cpp8114 Register FalseReg = MI->getOperand(2).getReg(); in createPHIsForSelects() local
8120 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
8125 if (RegRewriteTable.contains(FalseReg)) in createPHIsForSelects()
8126 FalseReg = RegRewriteTable[FalseReg].second; in createPHIsForSelects()
8131 .addReg(FalseReg).addMBB(FalseMBB); in createPHIsForSelects()
8134 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp788 auto FalseReg = MIB.getReg(3); in selectSelect() local
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
795 .addUse(FalseReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2354 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
2357 const TargetRegisterClass *FalseClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
2390 FalseReg.setImplicit(); in optimizeSelect()
2391 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h367 Register TrueReg, Register FalseReg, int &CondCycles,
373 Register TrueReg, Register FalseReg) const override;
378 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1245 .addReg(FalseReg) in insertVectorSelect()
1260 .addReg(FalseReg) in insertVectorSelect()
1274 .addReg(FalseReg) in insertVectorSelect()
1288 .addReg(FalseReg) in insertVectorSelect()
1304 .addReg(FalseReg) in insertVectorSelect()
1320 .addReg(FalseReg) in insertVectorSelect()
1338 .addReg(FalseReg) in insertVectorSelect()
3219 std::swap(TrueReg, FalseReg); in insertSelect()
3231 .addReg(FalseReg); in insertSelect()
3235 .addReg(FalseReg) in insertSelect()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h910 Register TrueReg, Register FalseReg, in canInsertSelect() argument
934 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h258 Register FalseReg) const override;
H A DAArch64InstrInfo.cpp701 Register FalseReg, int &CondCycles, in canInsertSelect() argument
707 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
729 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
751 Register TrueReg, Register FalseReg) const { in insertSelect()
859 TrueReg = FalseReg; in insertSelect()
861 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
865 FalseReg = NewVReg; in insertSelect()
874 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
879 .addReg(FalseReg) in insertSelect()