| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVAsmBackend.cpp | 474 unsigned Hi1 = (Value >> 11) & 0x1; in adjustFixupValue() local
481 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7); in adjustFixupValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 748 SDValue Hi1 = Node->getOperand(1); in trySelect() local
753 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5111 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
5125 (AND Shift1.Left, MaskValues.Hi1));
5179 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32));
5188 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA);
5197 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1));
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 840 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in SelectADD_SUB_I64() local
864 SDValue(Hi1, 0), in SelectADD_SUB_I64()
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| H A D | AMDGPUInstructionSelector.cpp | 373 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB() local
384 .add(Hi1) in selectG_ADD_SUB()
397 .add(Hi1) in selectG_ADD_SUB()
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| H A D | SIISelLowering.cpp | 5476 SDValue Lo1, Hi1; in splitBinaryVectorOp() local
5477 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1); in splitBinaryVectorOp()
5483 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, in splitBinaryVectorOp()
5505 SDValue Lo1, Hi1; in splitTernaryVectorOp() local
5506 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1); in splitTernaryVectorOp()
5515 SDValue OpHi = DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, in splitTernaryVectorOp()
10245 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); in LowerSELECT() local
10247 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1); in LowerSELECT()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 3923 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; in SplitVecOp_VSETCC() local
3926 GetSplitVector(N->getOperand(1), Lo1, Hi1); in SplitVecOp_VSETCC()
3935 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
3944 HiRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Hi0, Hi1, in SplitVecOp_VSETCC()
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| H A D | TargetLowering.cpp | 4992 SDValue Lo0, Lo1, Hi0, Hi1; in SimplifySetCC() local
4994 IsConcat(N0.getOperand(1), Lo1, Hi1)) { in SimplifySetCC()
4996 DAG.getNode(N0.getOpcode(), dl, OpVT, Hi0, Hi1)); in SimplifySetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9413 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); in isExtendedBUILD_VECTOR() local
9414 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) in isExtendedBUILD_VECTOR()
9418 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) in isExtendedBUILD_VECTOR()
9421 if (Hi0->isZero() && Hi1->isZero()) in isExtendedBUILD_VECTOR()
|