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/freebsd/crypto/openssl/crypto/ec/curve448/
H A Df_generic.c174 gf L0, L1, L2; in gf_isr() local
177 gf_mul(L2, x, L1); in gf_isr()
178 gf_sqr(L1, L2); in gf_isr()
179 gf_mul(L2, x, L1); in gf_isr()
180 gf_sqrn(L1, L2, 3); in gf_isr()
181 gf_mul(L0, L2, L1); in gf_isr()
183 gf_mul(L0, L2, L1); in gf_isr()
187 gf_mul(L2, x, L0); in gf_isr()
196 gf_sqr(L0, L2); in gf_isr()
200 gf_sqr(L2, L1); in gf_isr()
[all …]
/freebsd/lib/libc/i386/string/
H A Dstrcpy.S55 je L2
59 je L2
63 je L2
67 je L2
71 je L2
75 je L2
79 je L2
86 L2: popl %eax /* pop dst address */ label
H A Dstrcat.S65 je L2
69 je L2
73 je L2
77 je L2
81 je L2
85 je L2
89 je L2
96 L2: popl %eax /* pop destination address */ label
H A Dstrchr.S54 je L2
59 L2: label
H A Dstrrchr.S55 jne L2
57 L2: label
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A Dilist.h184 for (const_reference V : L2)
228 this->transferNodesFromList(L2, first, last);
230 base_list_type::splice(position, L2, first, last);
266 void splice(iterator where, iplist_impl &L2) {
267 if (!L2.empty())
268 transfer(where, L2, L2.begin(), L2.end());
273 transfer(where, L2, first, last);
276 if (first != last) transfer(where, L2, first, last);
279 splice(where, L2, iterator(N));
281 void splice(iterator where, iplist_impl &L2, pointer N) {
[all …]
H A Dsimple_ilist.h179 void cloneFrom(const simple_ilist &L2, Cloner clone, Disposer dispose) { in cloneFrom() argument
181 for (const_reference V : L2) in cloneFrom()
244 void splice(iterator I, simple_ilist &L2) { in splice() argument
245 splice(I, L2, L2.begin(), L2.end()); in splice()
249 void splice(iterator I, simple_ilist &L2, iterator Node) { in splice() argument
250 splice(I, L2, Node, std::next(Node)); in splice()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DLinkage.h129 inline Linkage minLinkage(Linkage L1, Linkage L2) { in minLinkage() argument
130 if (L2 == Linkage::VisibleNone) in minLinkage()
131 std::swap(L1, L2); in minLinkage()
133 if (L2 == Linkage::Internal) in minLinkage()
135 if (L2 == Linkage::UniqueExternal) in minLinkage()
138 return L1 < L2 ? L1 : L2; in minLinkage()
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
42 - reg : Address and size of L2 cache controller registers
43 - cache-size : Size of the entire L2 cache
44 - interrupts : Error interrupt of L2 controller
45 - cache-line-size : Size of L2 cache lines
49 L2: l2-cache-controller@20000 {
53 cache-size = <0x40000>; // L2,256K
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
42 - reg : Address and size of L2 cache controller registers
43 - cache-size : Size of the entire L2 cache
44 - interrupts : Error interrupt of L2 controller
45 - cache-line-size : Size of L2 cache lines
49 L2: l2-cache-controller@20000 {
53 cache-size = <0x40000>; // L2,256K
H A Dl2c2x0.yaml7 title: ARM L2 Cache Controller
15 implementations of the L2 cache controller have compatible programming
21 Note 1: The description in this document doesn't apply to integrated L2
23 integrated L2 controllers are assumed to be all preconfigured by
45 # maintenance operations on L1 are broadcasted to the L2 and L2
124 description: If present then L2 is forced to Write through mode
166 description: enable parity checking on the L2 cache (L220 or PL310).
174 description: enable ECC protection on the L2 cache
178 description: disable the outer sync operation on the L2 cache.
200 L2 dynamic clock gating. Value: <0> (forcibly
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/freebsd/contrib/libdiff/test/
H A Dexpect.results_test4 [0] same lines L2 R2 @L 0 @R 0
7 [3] same lines L2 R2 @L 5 @R 5
10 [0] same lines L2 R2 @L 0 @R 0
13 [3] same lines L2 R2 @L 5 @R 5
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dl2c2x0.yaml7 title: ARM L2 Cache Controller
15 implementations of the L2 cache controller have compatible programming
21 Note 1: The description in this document doesn't apply to integrated L2
23 integrated L2 controllers are assumed to be all preconfigured by
45 # maintenance operations on L1 are broadcasted to the L2 and L2
124 description: If present then L2 is forced to Write through mode
166 description: enable parity checking on the L2 cache (L220 or PL310).
174 description: enable ECC protection on the L2 cache
178 description: disable the outer sync operation on the L2 cache.
200 L2 dynamic clock gating. Value: <0> (forcibly
[all …]
/freebsd/crypto/openssl/crypto/whrlpool/
H A Dwp_block.c586 K.q[2] = L2; in whirlpool_block()
612 S.q[2] = L2; in whirlpool_block()
621 L2 = C2(K, 0); in whirlpool_block()
630 L2 ^= C1(K, 1); in whirlpool_block()
638 L2 ^= C0(K, 2); in whirlpool_block()
654 L2 ^= C7(K, 3); in whirlpool_block()
662 L2 ^= C6(K, 4); in whirlpool_block()
670 L2 ^= C5(K, 5); in whirlpool_block()
678 L2 ^= C4(K, 6); in whirlpool_block()
694 K.q[2] = L2; in whirlpool_block()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Dhighbank.dts25 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
135 L2: cache-controller { label
/freebsd/libexec/rtld-elf/arm/
H A Drtld_start.S42 ldr sl, .L2
43 ldr r5, .L2+4
44 ldr r0, .L2+8
64 .L2: label
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-dt.txt33 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca9.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
164 L2: cache-controller@1e00a000 { label
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
H A Darm-realview-eb-a9mp.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
H A Darm-realview-eb-11mp.dts46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
60 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
/freebsd/sys/contrib/device-tree/Bindings/arm/calxeda/
H A Dl2ecc.yaml7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
11 This does not cover the actual L2 cache controller control registers,
/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2.yaml35 next-level-cache = <&L2>;
46 next-level-cache = <&L2>;
92 next-level-cache = <&L2>;
103 next-level-cache = <&L2>;
114 next-level-cache = <&L2>;
125 next-level-cache = <&L2>;
176 next-level-cache = <&L2>;
187 next-level-cache = <&L2>;
198 next-level-cache = <&L2>;
209 next-level-cache = <&L2>;
/freebsd/contrib/llvm-project/clang/include/clang/Analysis/FlowSensitive/
H A DDataflowAnalysis.h102 const Lattice &L2 = llvm::any_cast<const Lattice &>(E2.Value); in joinTypeErased() local
103 L1.join(L2); in joinTypeErased()
117 const Lattice &L2 = llvm::any_cast<const Lattice &>(E2.Value); in isEqualTypeErased() local
118 return L1 == L2; in isEqualTypeErased()
/freebsd/sys/dev/iavf/
H A Diavf_common.c598 IAVF_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
599 IAVF_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
600 IAVF_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
603 IAVF_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
604 IAVF_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
607 IAVF_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
608 IAVF_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
609 IAVF_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
610 IAVF_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
611 IAVF_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610.dtsi8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label

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