| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
88 unsigned Lane, unsigned ToInsert);
416 unsigned Lane, bool QPR) { in createDupLane() argument
422 .addImm(Lane) in createDupLane()
431 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
438 .addReg(DReg, 0, Lane); in createExtractSubreg()
484 .addImm(Lane); in createInsertSubreg()
541 unsigned Lane; in optimizeAllLanesPattern() local
543 case ARM::ssub_0: Lane = 0; break; in optimizeAllLanesPattern()
544 case ARM::ssub_1: Lane = 1; break; in optimizeAllLanesPattern()
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp-db.dts | 192 /* Port 0, Lane 0 */
196 /* Port 0, Lane 1 */
200 /* Port 0, Lane 2 */
204 /* Port 0, Lane 3 */
208 /* Port 2, Lane 0 */
212 /* Port 3, Lane 0 */
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| H A D | armada-xp-axpwifiap.dts | 100 /* Port 0, Lane 0 */
106 /* Port 0, Lane 1 */
112 /* Port 0, Lane 3 */
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| H A D | armada-395-gp.dts | 86 /* Port 1, Lane 0 */
92 /* Port 3, Lane 0 */
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| H A D | armada-385-db-ap.dts | 156 /* Port 0, Lane 0 */
161 /* Port 1, Lane 0 */
166 /* Port 2, Lane 0 */
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| H A D | armada-xp-gp.dts | 189 /* Port 0, Lane 0 */
193 /* Port 2, Lane 0 */
197 /* Port 3, Lane 0 */
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| H A D | armada-370-mirabox.dts | 120 /* Port 0, Lane 0 */
126 /* Port 1, Lane 0 */
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| H A D | armada-375-db.dts | 46 /* Port 0, Lane 0 */
51 /* Port 1, Lane 0 */
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| H A D | armada-xp-netgear-rn2120.dts | 199 /* Port 0, Lane 0 */
205 /* Port 0, Lane 1 */
211 /* Port 1, Lane 0 */
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| H A D | armada-xp-linksys-mamba.dts | 218 /* Port 0, Lane 0 */
224 /* Port 0, Lane 1 */
230 /* Port 0, Lane 3 */
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| H A D | armada-388-db.dts | 133 /* Port 0, Lane 0 */
137 /* Port 1, Lane 0 */
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | hisilicon,kirin-pcie.yaml | 132 pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
140 pcie@0,0 { // Lane 0: upstream
148 pcie@1,0 { // Lane 4: M.2
158 pcie@5,0 { // Lane 5: Mini PCIe
168 pcie@7,0 { // Lane 6: Ethernet
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanSLP.cpp | 313 for (unsigned Lane = 1, E = MultiNodeOps[0].second.size(); Lane < E; ++Lane) { in reorderMultiNodeOps() local
314 LLVM_DEBUG(dbgs() << " Finding best value for lane " << Lane << "\n"); in reorderMultiNodeOps()
319 dbgs() << *cast<VPInstruction>(Ops.second[Lane])->getUnderlyingInstr() in reorderMultiNodeOps()
321 Candidates.insert(Ops.second[Lane]); in reorderMultiNodeOps()
330 VPValue *Last = FinalOrder[Op].second[Lane - 1]; in reorderMultiNodeOps()
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| H A D | VPlan.cpp | 72 Builder.getInt32(VF.getKnownMinValue() - Lane)); in getAsRuntimeExpr()
74 return Builder.getInt32(Lane); in getAsRuntimeExpr()
227 assert(Instance.Lane.isFirstLane() && "cannot get lane > 0 for scalar"); in get()
231 Value *Lane = Instance.Lane.getAsRuntimeExpr(Builder, VF); in get() local
232 auto *Extract = Builder.CreateExtractElement(VecPart, Lane); in get()
321 for (unsigned Lane = 0; Lane < VF.getKnownMinValue(); ++Lane) in get() local
322 packScalarIntoVectorValue(Def, {Part, Lane}); in get()
388 VectorValue, ScalarInst, Instance.Lane.getAsRuntimeExpr(Builder, VF)); in packScalarIntoVectorValue()
661 for (unsigned Lane = 0, VF = State->VF.getKnownMinValue(); Lane < VF; in execute() local
662 ++Lane) { in execute()
[all …]
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| H A D | VPlan.h | 159 unsigned Lane;
165 VPLane(unsigned Lane, Kind LaneKind) : Lane(Lane), LaneKind(LaneKind) {} in VPLane() argument
185 return Lane; in getKnownLane()
203 return VF.getKnownMinValue() + Lane; in mapToCacheIndex()
205 assert(Lane < VF.getKnownMinValue()); in mapToCacheIndex()
206 return Lane; in mapToCacheIndex()
223 VPLane Lane; member
225 VPIteration(unsigned Part, unsigned Lane,
227 : Part(Part), Lane(Lane, Kind) {} in Part()
229 VPIteration(unsigned Part, const VPLane &Lane) : Part(Part), Lane(Lane) {} in VPIteration()
[all …]
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| H A D | SLPVectorizer.cpp | 1580 ++Lane) in clearUsed()
1586 std::swap(OpsVec[OpIdx1][Lane], OpsVec[OpIdx2][Lane]); in swap()
1922 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in appendOperandsOfVL() local
2000 for (unsigned Lane = 0, Lanes = getNumLanes(); Lane != Lanes; ++Lane) in getVL() local
2001 OpVL[Lane] = OpsVec[OpIdx][Lane].V; in getVL()
2103 if (Lane < 0 || Lane >= (int)NumLanes) in reorder()
2635 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in setOperandsInOrder() local
2968 int Lane; member
4911 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { in buildExternalUses() local
11929 Value *Lane = Builder.getInt32(ExternalUse.Lane); in vectorizeTree() local
[all …]
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| H A D | VPlanRecipes.cpp | 173 auto Lane = VPLane::getLastLaneForVF(State.VF); in fixPhi() local
176 Lane = VPLane::getFirstLane(); in fixPhi()
182 Phi->addIncoming(State.get(ExitValue, VPIteration(State.UF - 1, Lane)), in fixPhi()
1165 StartLane = State.Instance->Lane.getKnownLane(); in execute()
1187 for (unsigned Lane = StartLane; Lane < EndLane; ++Lane) { in execute() local
1189 AddOp, StartIdx0, getSignedIntOrFpConstant(BaseIVTy, Lane)); in execute()
1197 State.set(this, Add, VPIteration(Part, Lane)); in execute()
1478 unsigned Lane = State.Instance->Lane.getKnownLane(); in execute() local
1486 ConditionBit, State.Builder.getInt32(Lane)); in execute()
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| /freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 245 /* CPM Lane 5 - U29 */
292 /* CPS Lane 0 - J5 (Gigabit RJ45) */
302 /* CPS Lane 5 */
345 /* CPS Lane 1 - U32 */
351 /* CPS Lane 3 - U31 */
382 /* CPS Lane 2 - CON7 */
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | phy-mvebu-comphy.txt | 20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | LaneBitmask.h | 83 static constexpr LaneBitmask getLane(unsigned Lane) { in getLane()
84 return LaneBitmask(Type(1) << Lane); in getLane()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2096 return Lane->getOperand(0); in LowerBUILD_VECTOR()
2130 if (Lane.isUndef()) in LowerBUILD_VECTOR()
2133 AddCount(SplatValueCounts, Lane); in LowerBUILD_VECTOR()
2135 if (IsConstant(Lane)) in LowerBUILD_VECTOR()
2213 SDValue Src = GetShuffleSrc(Lane); in LowerBUILD_VECTOR()
2225 auto Src = GetShuffleSrc(Lane); in LowerBUILD_VECTOR()
2231 if (IsConstant(Lane)) { in LowerBUILD_VECTOR()
2248 ConstLanes.push_back(Lane); in LowerBUILD_VECTOR()
2258 return IsConstant(Lane); in LowerBUILD_VECTOR()
2264 return Lane == SplatValue; in LowerBUILD_VECTOR()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 441 for (int Lane = 0; Lane < LaneCount; Lane++) in createShuffleStride() local
443 Mask.push_back((i * Stride) % LaneSize + LaneSize * Lane); in createShuffleStride()
613 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle() local
615 IndexGroup[(Index * 3) % (VF / Lane)] = Index; in group2Shuffle()
619 for (int i = 0; i < VF / Lane; i++) { in group2Shuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 313 bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI, in matchDupFromInsertVectorElt() argument
316 if (Lane != 0) in matchDupFromInsertVectorElt()
353 bool matchDupFromBuildVector(int Lane, MachineInstr &MI, in matchDupFromBuildVector() argument
356 assert(Lane >= 0 && "Expected positive lane?"); in matchDupFromBuildVector()
363 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg(); in matchDupFromBuildVector()
375 int Lane = *MaybeLane; in matchDup() local
377 if (Lane < 0) in matchDup()
378 Lane = 0; in matchDup()
379 if (matchDupFromInsertVectorElt(Lane, MI, MRI, MatchInfo)) in matchDup()
381 if (matchDupFromBuildVector(Lane, MI, MRI, MatchInfo)) in matchDup()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 58 int Lane = -1; member
61 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} in SpilledReg()
63 bool hasLane() { return Lane != -1; } in hasLane()
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sc7180-trogdor-lazor-r0.dts | 21 * Lane 0 was incorrectly mapped on the cable, but we've now decided
|