| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 92 ADD_VVP_OP(VVP_GATHER, MGATHER) HANDLE_VP_TO_VVP(VP_GATHER, VVP_GATHER)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1291 MGATHER, enumerator
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| H A D | SelectionDAGNodes.h | 1409 case ISD::MGATHER:
1449 case ISD::MGATHER:
2873 return N->getOpcode() == ISD::MGATHER ||
2887 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
2899 return N->getOpcode() == ISD::MGATHER;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 887 MGATHER, enumerator
1847 return N->getOpcode() == X86ISD::MGATHER || in classof()
1857 return N->getOpcode() == X86ISD::MGATHER; in classof()
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| H A D | X86ISelLowering.cpp | 1605 setOperationAction(ISD::MGATHER, MVT::v2f32, Custom); in X86TargetLowering()
1606 setOperationAction(ISD::MGATHER, MVT::v2i32, Custom); in X86TargetLowering()
1610 setOperationAction(ISD::MGATHER, VT, Custom); in X86TargetLowering()
1954 setOperationAction(ISD::MGATHER, VT, Custom); in X86TargetLowering()
2477 ISD::MGATHER, in X86TargetLowering()
26314 DAG.getMemIntrinsicNode(X86ISD::MGATHER, dl, VTs, Ops, in getAVX2GatherNode()
26352 DAG.getMemIntrinsicNode(X86ISD::MGATHER, dl, VTs, Ops, in getGatherNode()
33026 case ISD::MGATHER: { in ReplaceNodeResults()
33501 NODE_NAME_CASE(MGATHER) in getTargetNodeName()
56317 case X86ISD::MGATHER: in PerformDAGCombine()
[all …]
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| H A D | X86ISelDAGToDAG.cpp | 6190 case X86ISD::MGATHER: { in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 410 case ISD::MGATHER: return "masked_gather"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 1028 case ISD::MGATHER: in SplitVectorResult()
3003 case ISD::MGATHER: in SplitVectorOperand()
4112 case ISD::MGATHER: in WidenVectorResult()
6047 case ISD::MGATHER: Res = WidenVecOp_MGATHER(N, OpNo); break; in WidenVectorOperand()
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| H A D | LegalizeVectorOps.cpp | 442 case ISD::MGATHER: in LegalizeOp()
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| H A D | LegalizeIntegerTypes.cpp | 84 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N)); in PromoteIntegerResult()
1809 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N), in PromoteIntegerOperand()
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| H A D | SelectionDAG.cpp | 872 case ISD::MGATHER: { in AddNodeIDCustom()
9444 AddNodeIDNode(ID, ISD::MGATHER, VTs, Ops); in getMaskedGather()
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| H A D | DAGCombiner.cpp | 2047 case ISD::MGATHER: return visitMGATHER(N); in visit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 837 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
975 setOperationAction({ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1169 {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); in RISCVTargetLowering()
1282 ISD::MGATHER, ISD::MSCATTER}, in RISCVTargetLowering()
1400 setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER, in RISCVTargetLowering()
6630 case ISD::MGATHER: in LowerOperation()
15541 case ISD::MGATHER: { in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1015 setTargetDAGCombine({ISD::MGATHER, ISD::MSCATTER}); in AArch64TargetLowering()
1306 setOperationAction(ISD::MGATHER, VT, Custom); in AArch64TargetLowering()
1410 setOperationAction(ISD::MGATHER, VT, Custom); in AArch64TargetLowering()
1452 setOperationAction(ISD::MGATHER, VT, Custom); in AArch64TargetLowering()
1523 setOperationAction(ISD::MGATHER, VT, Custom); in AArch64TargetLowering()
1897 setOperationAction(ISD::MGATHER, VT, StreamingSVE ? Expand : Custom); in addTypeForFixedLengthSVE()
6294 case ISD::MGATHER: in LowerOperation()
23919 case ISD::MGATHER: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 718 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather,
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