/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrExtension.td | 39 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), 47 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src), 55 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), 65 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src), 73 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), 81 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), 94 def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 97 def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 114 def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg, 124 def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg, [all …]
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H A D | X86InstrMMX.td | 37 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 55 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 93 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), 110 def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), 137 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), 233 def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), 238 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst), 248 def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), 472 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, 512 def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg, [all …]
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H A D | X86InstrKL.td | 20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), 26 def ENCODEKEY128 : I<0xFA, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 31 def ENCODEKEY256 : I<0xFB, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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H A D | X86InstrSSE.td | 1847 def rr : SIi8<0xC2, MRMSrcReg, 1969 def rri : PIi8<0xC2, MRMSrcReg, 2113 def rr : PI<opc, MRMSrcReg, 3740 def ri : Ii8<0x70, MRMSrcReg, 3775 def rr : PDI<opc, MRMSrcReg, 3800 def rr : SS48I<opc, MRMSrcReg, 3876 def rr : PDI<opc, MRMSrcReg, 3979 def rr : Ii8<0xC4, MRMSrcReg, 4002 def VPEXTRWrr : Ii8<0xC5, MRMSrcReg, 4545 def rr : I<0xD0, MRMSrcReg, [all …]
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H A D | X86InstrXOP.td | 14 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 45 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 56 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), 67 def Yrr : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), 118 def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst), 142 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), 171 def rr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst), 248 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), 284 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst), 331 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst), [all …]
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H A D | X86InstrSystem.td | 34 def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2), 36 def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2), 38 def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2), 133 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), 136 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), 152 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), 155 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), 198 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), 200 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), 440 def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), [all …]
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H A D | X86InstrFMA.td | 39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 80 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 181 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst), 202 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst), 222 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst), 272 def r_Int : FMA3S_Int<opc, MRMSrcReg, (outs RC:$dst), 422 def rr_REV : FMA4S<opc, MRMSrcReg, (outs RC:$dst), 457 def rr_Int_REV : FMA4S_Int<opc, MRMSrcReg, (outs VR128:$dst), 526 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst), [all …]
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H A D | X86InstrVMX.td | 69 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 71 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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H A D | X86Instr3DNow.td | 32 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, 45 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
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H A D | X86InstrAVX512.td | 1195 defm rr : AVX512_maskable_custom<opc, MRMSrcReg, 1974 def rr : AVX512Ii8<0xC2, MRMSrcReg, 2014 def rr : AVX512BI<opc, MRMSrcReg, 2024 def rrk : AVX512BI<opc, MRMSrcReg, 2132 def rri : AVX512AIi8<opc, MRMSrcReg, 2151 def rrik : AVX512AIi8<opc, MRMSrcReg, 5367 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), 5413 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), 5492 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), 11530 def rr : AVX512BI<opc, MRMSrcReg, [all …]
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H A D | X86InstrMisc.td | 251 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 259 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 267 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 276 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 284 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 292 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 855 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), 858 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), 862 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), 866 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), [all …]
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H A D | X86InstrArithmetic.td | 199 let Form = MRMSrcReg; 206 let Form = MRMSrcReg; 263 : BinOpRI8<0x6B, "imul", binop_ndd_args, t, MRMSrcReg, 268 : BinOpRI<0x69, "imul", binop_ndd_args, t, MRMSrcReg, 273 : BinOpRI<0x69, "imul", binop_ndd_args, t, MRMSrcReg, 1322 def rr#suffix : ITy<0xF2, MRMSrcReg, t, (outs t.RegClass:$dst), 1370 def rr : ITy<0xF6, MRMSrcReg, t, (outs t.RegClass:$dst1, t.RegClass:$dst2), 1379 def rr_EVEX : ITy<0xF6, MRMSrcReg, t, 1409 let Form = MRMSrcReg in {
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H A D | X86InstrTBM.td | 23 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
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H A D | X86InstrFormats.td | 46 def MRMSrcReg : Format<41>;
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H A D | X86InstrUtils.td | 984 let Form = MRMSrcReg; 993 let Form = MRMSrcReg; 1004 let Form = MRMSrcReg; 1018 let Form = MRMSrcReg;
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H A D | X86InstrShiftRotate.td | 542 : ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2),
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | X86RecognizableInstr.h | 129 MRMSrcReg = 41, enumerator
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H A D | X86FoldTablesEmitter.cpp | 270 case X86Local::MRMSrcReg: in mayFoldFromForm() 319 case X86Local::MRMSrcReg: in mayFoldFromLeftToRight()
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H A D | X86RecognizableInstr.cpp | 138 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); in RecognizableInstrBase() 604 case X86Local::MRMSrcReg: in emitInstructionSpecifier() 867 case X86Local::MRMSrcReg: in emitDecodePath()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86BaseInfo.h | 595 MRMSrcReg = 41, enumerator 1050 case X86II::MRMSrcReg: in getMemoryOperandNo()
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H A D | X86MCCodeEmitter.cpp | 1170 case X86II::MRMSrcReg: { in emitVEXOpcodePrefix() 1351 case X86II::MRMSrcReg: in emitREXPrefix() 1643 case X86II::MRMSrcReg: { in encodeInstruction()
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H A D | X86EncodingOptimization.cpp | 40 (TSFlags & X86II::FormMask) != X86II::MRMSrcReg || in optimizeInstFromVEX3ToVEX2()
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