| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineInternal.h | 219 bool fmulByZeroIsZero(Value *MulVal, FastMathFlags FMF,
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| H A D | InstCombineCompares.cpp | 5816 static Instruction *processUMulZExtIdiom(ICmpInst &I, Value *MulVal, in processUMulZExtIdiom() argument
5821 if (!isa<IntegerType>(MulVal->getType())) in processUMulZExtIdiom()
5824 auto *MulInstr = dyn_cast<Instruction>(MulVal); in processUMulZExtIdiom()
5852 if (MulVal->hasNUsesOrMore(2)) in processUMulZExtIdiom()
5853 for (User *U : MulVal->users()) { in processUMulZExtIdiom()
5925 if (MulVal->hasNUsesOrMore(2)) { in processUMulZExtIdiom()
5927 for (User *U : make_early_inc_range(MulVal->users())) { in processUMulZExtIdiom()
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| H A D | InstCombineSelect.cpp | 3338 bool InstCombinerImpl::fmulByZeroIsZero(Value *MulVal, FastMathFlags FMF, in fmulByZeroIsZero() argument
3340 KnownFPClass Known = computeKnownFPClass(MulVal, FMF, fcNegative, CtxI); in fmulByZeroIsZero()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2530 SDValue MulVal = N.getOperand(0); in matchAddressRecursively() local
2536 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && in matchAddressRecursively()
2537 isa<ConstantSDNode>(MulVal.getOperand(1))) { in matchAddressRecursively()
2538 Reg = MulVal.getOperand(0); in matchAddressRecursively()
2539 auto *AddVal = cast<ConstantSDNode>(MulVal.getOperand(1)); in matchAddressRecursively()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4249 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N1, MulOper); in performMulCombine() local
4250 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N1); in performMulCombine()
4254 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N0, MulOper); in performMulCombine() local
4255 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N0); in performMulCombine()
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| H A D | AMDGPULegalizerInfo.cpp | 2729 auto MulVal = B.buildFMul(Ty, SrcReg, OneOver2Pi, Flags); in legalizeSinCos() local
2731 .addUse(MulVal.getReg(0)) in legalizeSinCos()
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| H A D | SIISelLowering.cpp | 10972 SDValue MulVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi, Flags); in LowerTrig() local
10973 TrigVal = DAG.getNode(AMDGPUISD::FRACT, DL, VT, MulVal, Flags); in LowerTrig()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 5451 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt; in TryMULWIDECombine() local
5452 RHS = DCI.DAG.getConstant(MulVal, DL, MulType); in TryMULWIDECombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12857 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N1, MulOper); in performMULCombine() local
12858 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performMULCombine()
12862 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper); in performMULCombine() local
12863 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMULCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17101 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N1, MulOper); in performMulCombine() local
17102 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performMulCombine()
17106 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper); in performMulCombine() local
17107 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMulCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4548 APInt MulVal; in visitMUL() local
4550 ISD::isConstantSplatVector(N1.getNode(), MulVal)) { in visitMUL()
4552 APInt NewStep = C0 * MulVal; in visitMUL()
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