| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.cpp | 419 if (OperandIdx >= MaxOperands) in getOperandAsUnsigned()
422 OperandIdx); in getOperandAsUnsigned()
424 uint64_t Operand = Ops[OperandIdx]; in getOperandAsUnsigned()
440 OperandIdx); in getOperandAsUnsigned()
454 OperandIdx); in getOperandAsUnsigned()
464 if (OperandIdx >= MaxOperands) in getOperandAsSigned()
467 OperandIdx); in getOperandAsSigned()
469 uint64_t Operand = Ops[OperandIdx]; in getOperandAsSigned()
485 OperandIdx, CFIProgram::operandTypeString(Type)); in getOperandAsSigned()
508 OperandIdx); in getOperandAsSigned()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600Packetizer.cpp | 81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector() local
82 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0) in getPreviousVector()
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Op); in substitutePV() local
132 if (OperandIdx < 0) in substitutePV()
134 Register Src = MI.getOperand(OperandIdx).getReg(); in substitutePV()
137 MI.getOperand(OperandIdx).setReg(It->second); in substitutePV()
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| H A D | GCNVOPDUtils.cpp | 69 auto getVRegIdx = [&](unsigned OpcodeIdx, unsigned OperandIdx) { in checkVOPDRegConstraints() argument
71 const MachineOperand &Operand = MI.getOperand(OperandIdx); in checkVOPDRegConstraints()
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| H A D | R600ISelLowering.cpp | 2085 int OperandIdx[] = { in PostISelFolding() local
2116 if (OperandIdx[i] < 0) in PostISelFolding()
2118 SDValue &Src = Ops[OperandIdx[i] - 1]; in PostISelFolding()
2122 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]); in PostISelFolding()
2138 int OperandIdx[] = { in PostISelFolding() local
2154 if (OperandIdx[i] < 0) in PostISelFolding()
2156 SDValue &Src = Ops[OperandIdx[i] - 1]; in PostISelFolding()
2161 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]); in PostISelFolding()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 169 unsigned OperandIdx) const { in getOperandCycle() argument
175 if ((FirstIdx + OperandIdx) >= LastIdx) in getOperandCycle()
178 return OperandCycles[FirstIdx + OperandIdx]; in getOperandCycle()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | CanonicalizeFreezeInLoops.cpp | 214 unsigned OperandIdx = in run() local
216 InsertFreezeAndForgetFromSCEV(PHI->getOperandUse(OperandIdx)); in run()
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| H A D | ScalarEvolutionExpander.cpp | 1905 WorkItem.ParentOpcode, WorkItem.OperandIdx, Imm, Ty, CostKind); in isHighCostExpansionHelper()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.h | 424 uint32_t OperandIdx) const;
427 uint32_t OperandIdx) const;
526 const Instruction &Instr, unsigned OperandIdx,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/ |
| H A D | ScalarEvolutionExpander.h | 35 ParentOpcode(Opc), OperandIdx(Idx), S(S) { } in SCEVOperand()
39 int OperandIdx; member
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineFunction.cpp | 1192 unsigned OperandIdx = 0; in finalizeDebugInstrRefs() local
1196 ++OperandIdx; in finalizeDebugInstrRefs()
1198 assert(OperandIdx < DefMI.getNumOperands()); in finalizeDebugInstrRefs()
1202 MO.ChangeToDbgInstrRef(ID, OperandIdx); in finalizeDebugInstrRefs()
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| H A D | CodeGenPrepare.cpp | 7620 unsigned OperandIdx) { in canCauseUndefinedBehavior() argument
7623 if (OperandIdx != 1) in canCauseUndefinedBehavior()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 869 unsigned OperandIdx = 0; in EmitDbgInstrRef() local
873 ++OperandIdx; in EmitDbgInstrRef()
875 assert(OperandIdx < DefMI->getNumOperands()); in EmitDbgInstrRef()
879 MOs.push_back(MachineOperand::CreateDbgInstrRef(InstrNum, OperandIdx)); in EmitDbgInstrRef()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | RewriteStatepointsForGC.cpp | 1222 auto UpdateOperand = [&](int OperandIdx) { in findBasePointer() argument
1223 Value *InVal = BdvIE->getOperand(OperandIdx); in findBasePointer()
1225 BaseIE->setOperand(OperandIdx, Base); in findBasePointer()
1232 auto UpdateOperand = [&](int OperandIdx) { in findBasePointer() argument
1233 Value *InVal = BdvSV->getOperand(OperandIdx); in findBasePointer()
1235 BaseSV->setOperand(OperandIdx, Base); in findBasePointer()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3638 auto getVRegIdx = [&](unsigned, unsigned OperandIdx) { in validateVOPDRegBankConstraints() argument
3639 const MCOperand &Opr = Inst.getOperand(OperandIdx); in validateVOPDRegBankConstraints()
6781 unsigned OperandIdx[4]; in cvtExp() local
6791 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
6799 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
6822 Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]); in cvtExp()
6823 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); in cvtExp()
6824 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); in cvtExp()
6828 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) { in cvtExp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1689 unsigned OperandIdx = Commuted ? 2 : 1; in hasReassociableSibling() local
1691 *MRI.getVRegDef(Inst.getOperand(OperandIdx).getReg()); in hasReassociableSibling()
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| H A D | RISCVISelLowering.cpp | 13297 NodeExtensionHelper(SDNode *Root, unsigned OperandIdx, SelectionDAG &DAG, in NodeExtensionHelper()
13301 assert(OperandIdx < 2 && "Requesting something else than LHS or RHS"); in NodeExtensionHelper()
13302 OrigOperand = Root->getOperand(OperandIdx); in NodeExtensionHelper()
13312 if (OperandIdx == 1) { in NodeExtensionHelper()
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