| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 219 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
230 const MachineOperand &PredOp, bool Cond,
646 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
660 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor()
669 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
674 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
879 const MachineOperand &PredOp, bool Cond, in predicateAt() argument
908 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, in predicateAt()
909 PredOp.getSubReg()); in predicateAt()
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| H A D | HexagonGenMux.cpp | 239 MachineOperand &PredOp = MI.getOperand(1); in genMuxInBlock() local
240 if (PredOp.isUndef()) in genMuxInBlock()
243 Register PR = PredOp.getReg(); in genMuxInBlock()
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| H A D | HexagonISelLowering.cpp | 1089 SDValue PredOp = Op.getOperand(0); in LowerVSELECT() local
1101 DAG.getSelect(dl, WideTy, PredOp, in LowerVSELECT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrCDE.td | 94 dag PredOp; // Input predicate operand
115 !con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
131 !con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
149 !con(params.Iops3, (ins imm_6b:$imm), params.PredOp),
191 let PredOp = !if(acc, (ins pred:$p), (ins));
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 535 MachineOperand &PredOp = ICMP->getOperand(1); in processSwitches() local
536 const auto CC = static_cast<CmpInst::Predicate>(PredOp.getPredicate()); in processSwitches()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1789 auto PredOp = ICmp.getOperand(1); in selectCompareBranchFedByICmp() local
1790 emitIntegerCompare(ICmp.getOperand(2), ICmp.getOperand(3), PredOp, MIB); in selectCompareBranchFedByICmp()
1792 static_cast<CmpInst::Predicate>(PredOp.getPredicate())); in selectCompareBranchFedByICmp()
2363 auto &PredOp = Cmp->getOperand(1); in earlySelect() local
2364 auto Pred = static_cast<CmpInst::Predicate>(PredOp.getPredicate()); in earlySelect()
2369 /*RHS=*/Cmp->getOperand(3), PredOp, MIB); in earlySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 837 auto PredOp = PredIntr->getOperand(0); in tryCombineFromSVBoolBinOp() local
838 auto PredOpTy = cast<VectorType>(PredOp->getType()); in tryCombineFromSVBoolBinOp()
842 SmallVector<Value *> NarrowedBinOpArgs = {PredOp}; in tryCombineFromSVBoolBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 3338 MachineOperand &PredOp = Def->getOperand(1); in applyNotCmp() local
3340 (CmpInst::Predicate)PredOp.getPredicate()); in applyNotCmp()
3341 PredOp.setPredicate(NewP); in applyNotCmp()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 21042 const Expr *PredOp = E->getArg(0); in EmitHexagonBuiltinExpr() local
21044 if (auto *Cast = dyn_cast<ImplicitCastExpr>(PredOp)) { in EmitHexagonBuiltinExpr()
21046 PredOp = Cast->getSubExpr(); in EmitHexagonBuiltinExpr()
21047 Ops.push_back(V2Q(EmitScalarExpr(PredOp))); in EmitHexagonBuiltinExpr()
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