| /freebsd/contrib/llvm-project/lldb/source/Plugins/Process/gdb-remote/ |
| H A D | GDBRemoteRegisterFallback.cpp | 22 #define R16(name) REG(name, 2) macro
44 R16(pc), R16(sp), R16(r2), R16(r3), R16(fp), R16(r5), in GetRegisters_msp430()
45 R16(r6), R16(r7), R16(r8), R16(r9), R16(r10), R16(r11), in GetRegisters_msp430()
46 R16(r12), R16(r13), R16(r14), R16(r15)}; in GetRegisters_msp430()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.td | 52 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
87 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
103 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
137 R28, R29, R17, R16)>;
141 (add R23, R22, R21, R20, R19, R18, R17, R16)>;
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| H A D | AVRSubtarget.h | 92 return hasTinyEncoding() ? AVR::R16 : AVR::R0; in getTmpRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYInstPrinter.cpp | 247 printRegName(O, CSKY::R16); in printRegisterList()
253 printRegName(O, CSKY::R16 + Offset); in printRegisterList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiBaseInfo.h | 81 case Lanai::R16: in getLanaiRegisterNumbering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiRegisterInfo.td | 46 (add R3, R9, R12, R13, R14, R16, R17,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 121 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
130 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
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| H A D | HexagonFrameLowering.h | 93 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
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| H A D | HexagonRegisterInfo.td | 145 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
539 (add R23, R22, R21, R20, R19, R18, R17, R16,
643 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 348 if (from != CSKY::R4 && from != CSKY::R15 && from != CSKY::R16 && in isLegalRegList()
354 if (from != CSKY::R4 && from != CSKY::R16) in isLegalRegList()
359 else if (from == CSKY::R16 && to > CSKY::R16 && to < CSKY::R18) in isLegalRegList()
592 else if (ListFrom == CSKY::R16) in getListValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 300 ENTRY(R16) \
334 ENTRY(R16) \
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYRegisterInfo.cpp | 68 markSuperRegs(Reserved, CSKY::R16 + i); // R16 - R25 in getReservedRegs()
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| H A D | CSKYRegisterInfo.td | 68 def R16 : CSKYReg<16, "r16", ["l8"]>, DwarfRegNum<[16]>;
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| H A D | CSKYInstrInfo.cpp | 504 assert(DestReg < CSKY::R16); in copyPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 1183 assert(X86::R31WH - X86::R16 == 95 && "EGPRs are not continuous"); in isApxExtendedReg()
1184 return RegNo >= X86::R16 && RegNo <= X86::R31WH; in isApxExtendedReg()
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| /freebsd/sys/contrib/device-tree/src/arm/allwinner/ |
| H A D | sun8i-r16-parrot.dts | 53 model = "Allwinner R16 EVB (Parrot)";
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 302 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
324 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 621 Reserved.set(X86::R16, X86::R31WH + 1); in getReservedRegs()
649 (X86::K6_K7 + 1 == X86::TMMCFG) && (X86::TMM7 + 1 == X86::R16) && in getNumSupportedRegs()
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| H A D | X86RegisterInfo.td | 91 // and regression. We don't know if we should assign cost to R16-R31 w/o
302 def R16 : X86Reg<"r16", 16, [R16D]>, DwarfRegNum<[130, -2, -2]>;
586 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 127 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchRegisterInfo.td | 76 def R16 : LoongArchReg<16, "r16", ["t4"]>, DwarfRegNum<[16]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 562 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeIntRegsRegisterClass()
577 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeGeneralSubRegsRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 291 case R16: in getDuplexRegisterNumbering()
666 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23)); in isIntRegForSubInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 65 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
|