Searched refs:R_P0_TXPW_RSTB (Results 1 – 5 of 5) sorted by relevance
/freebsd/sys/contrib/dev/rtw89/ |
H A D | rtw8852c.c | 1684 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); in rtw8852c_set_channel_bb() 1685 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); in rtw8852c_set_channel_bb() 1692 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); in rtw8852c_set_channel_bb() 1693 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); in rtw8852c_set_channel_bb() 2091 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); in rtw8852c_bb_cfg_rx_path() 2092 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); in rtw8852c_bb_cfg_rx_path() 2111 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, in rtw8852c_bb_cfg_rx_path() 2113 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, in rtw8852c_bb_cfg_rx_path() 2150 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, in rtw8852c_bb_cfg_rx_path() 2152 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, in rtw8852c_bb_cfg_rx_path()
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H A D | rtw8852a.c | 1117 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); in rtw8852a_bb_reset() 1122 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); in rtw8852a_bb_reset() 1149 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); in rtw8852a_bb_sethw() 1601 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); in rtw8852a_bb_cfg_tx_path() 1602 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); in rtw8852a_bb_cfg_tx_path()
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H A D | rtw8851b.c | 1375 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, in rtw8851b_bb_reset() 1379 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, in rtw8851b_bb_reset() 1504 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0); in rtw8851b_tssi_cont_en() 1507 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1); in rtw8851b_tssi_cont_en() 1870 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); in rtw8851b_bb_ctrl_rx_path() 1871 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); in rtw8851b_bb_ctrl_rx_path()
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H A D | rtw8852b.c | 1389 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); in rtw8852b_bb_reset() 1394 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); in rtw8852b_bb_reset() 1481 static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB}; in rtw8852b_tssi_cont_en() 2029 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); in rtw8852b_bb_ctrl_rx_path() 2030 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); in rtw8852b_bb_ctrl_rx_path()
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H A D | reg.h | 4574 #define R_P0_TXPW_RSTB 0x58DC macro
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