| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 30 const RegisterClassInfo &RegClassInfo, in create() argument
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
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| H A D | BreakFalseDeps.cpp | 41 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
289 RegClassInfo.runOnMachineFunction(mf); in runOnMachineFunction()
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| H A D | RegAllocEvictionAdvisor.cpp | 130 RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)), in RegAllocEvictionAdvisor()
234 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in canEvictInterferenceBasedOnCost()
235 RegClassInfo.getNumAllocatableRegs( in canEvictInterferenceBasedOnCost()
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| H A D | RegAllocBase.cpp | 65 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
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| H A D | RegAllocBase.h | 70 RegisterClassInfo RegClassInfo; variable
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| H A D | CriticalAntiDepBreaker.h | 41 const RegisterClassInfo &RegClassInfo; variable
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| H A D | RegAllocGreedy.cpp | 329 (2 * RegClassInfo.getNumAllocatableRegs(&RC))); in getPriority()
466 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) { in canReassign()
525 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
541 uint8_t MinCost = RegClassInfo.getMinCost(RC); in getOrderLimit()
551 OrderLimit = RegClassInfo.getLastCostChange(RC); in getOrderLimit()
568 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in canAllocatePhysReg()
937 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
1300 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
1423 if (!RegClassInfo.isProperSubClass(CurRC)) { in tryInstructionSplit()
1444 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
[all …]
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| H A D | RegAllocPriorityAdvisor.h | 43 const RegisterClassInfo &RegClassInfo; variable
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| H A D | RegAllocFast.cpp | 191 RegisterClassInfo RegClassInfo; member in __anon270390b30111::RegAllocFast
911 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
966 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
1044 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in defineVirtReg()
1135 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1310 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in findAndSortDefOperandIndexes()
1311 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in findAndSortDefOperandIndexes()
1744 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | PostRASchedulerList.cpp | 78 RegisterClassInfo RegClassInfo; member in __anon30b9b1f00111::PostRAScheduler
286 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
309 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
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| H A D | AllocationOrder.h | 85 const RegisterClassInfo &RegClassInfo,
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| H A D | RegAllocPriorityAdvisor.cpp | 109 RegClassInfo(RA.getRegClassInfo()), Indexes(Indexes), in RegAllocPriorityAdvisor()
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| H A D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; variable
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| H A D | RegAllocEvictionAdvisor.h | 144 const RegisterClassInfo &RegClassInfo; variable
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| H A D | MachineCombiner.cpp | 76 RegisterClassInfo RegClassInfo; member in __anon6093efe00111::MachineCombiner
592 TII->shouldReduceRegisterPressure(MBB, &RegClassInfo); in combineInstructions()
752 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | CriticalAntiDepBreaker.cpp | 44 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
399 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | RegAllocBasic.cpp | 266 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
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| H A D | MachineScheduler.cpp | 189 RegClassInfo = new RegisterClassInfo(); in MachineSchedContext()
193 delete RegClassInfo; in ~MachineSchedContext()
438 RegClassInfo->runOnMachineFunction(*MF); in runOnMachineFunction()
1225 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, in initRegPressure()
1227 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in initRegPressure()
1279 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
1309 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
1492 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in buildDAGWithRegPressure()
3254 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
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| H A D | AggressiveAntiDepBreaker.cpp | 124 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
609 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 45 RegisterClassInfo RegClassInfo; member in __anon62a010af0111::SIPreAllocateWWMRegs
105 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
204 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | SIMachineScheduler.h | 445 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 240 struct RegClassInfo { struct
252 const RegClassInfo *const RCInfos; argument
263 const RegClassInfo *const RCIs,
773 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { in getRegClassInfo()
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| H A D | MachineScheduler.h | 136 RegisterClassInfo *RegClassInfo; member
400 RegisterClassInfo *RegClassInfo;
440 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
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| H A D | MachinePipeliner.h | 74 RegisterClassInfo RegClassInfo; variable
124 const RegisterClassInfo &RegClassInfo; variable
208 RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI), in SwingSchedulerDAG()
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| H A D | VLIWMachineScheduler.h | 80 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; } in getRegClassInfo()
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