/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 435 IMPLEMENT_SCALAR_NANS(Ty, Src1, Src2) in executeFCMP_ONE() 536 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UEQ() 546 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UNE() 555 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_ULE() 564 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UGE() 573 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_ULT() 582 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UGT() 610 Dest.IntVal = APInt(1,(Src1.FloatVal == Src1.FloatVal && in executeFCMP_ORD() 613 Dest.IntVal = APInt(1,(Src1.DoubleVal == Src1.DoubleVal && in executeFCMP_ORD() 641 Dest.IntVal = APInt(1,(Src1.FloatVal != Src1.FloatVal || in executeFCMP_UNO() [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.h | 1564 const SrcOp &Src1, 1581 const SrcOp &Src1, 1597 const SrcOp &Src1, 1616 const SrcOp &Src1, 1622 const SrcOp &Src1, 1652 const SrcOp &Src1, 1658 const SrcOp &Src1, 1664 const SrcOp &Src1, 1696 const SrcOp &Src1, 1755 const SrcOp &Src1, [all …]
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H A D | GISelKnownBits.h | 38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known, 42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
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H A D | MIPatternMatch.h | 729 Src1Ty Src1; 732 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) 733 : Src0(Src0), Src1(Src1), Src2(Src2) {} 740 Src1.match(MRI, TmpMI->getOperand(2).getReg()) && 750 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) { 752 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2); 757 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) { 759 Src0, Src1, Src2);
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ExpandSpecialInstrs.cpp | 149 Register Src1 = in runOnMachineFunction() local 153 (void) Src1; in runOnMachineFunction() 155 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction() 156 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction() 200 unsigned Src1 = 0; in runOnMachineFunction() local 206 Src1 = MI.getOperand(Src1Idx).getReg(); in runOnMachineFunction() 212 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction() 217 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction() 252 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
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H A D | AMDGPUInstCombineIntrinsic.cpp | 52 return maxnum(Src1, Src2); in fmed3AMDGCN() 59 return maxnum(Src0, Src1); in fmed3AMDGCN() 606 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local 629 Src1, ConstantInt::getNullValue(Src1->getType())); in instCombineIntrinsic() 636 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local 777 } else if (match(Src1, PatternMatch::m_NaN()) || isa<UndefValue>(Src1)) { in instCombineIntrinsic() 794 std::swap(Src0, Src1); in instCombineIntrinsic() 799 std::swap(Src1, Src2); in instCombineIntrinsic() 804 std::swap(Src0, Src1); in instCombineIntrinsic() 810 II.setArgOperand(1, Src1); in instCombineIntrinsic() [all …]
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H A D | SIOptimizeExecMasking.cpp | 144 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec() 160 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec() 542 OtherOp = &Src1; in optimizeExecSequence() 543 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) { in optimizeExecSequence() 612 Builder.add(*Src1); in optimizeVCMPSaveExecSequence() 619 if (Src1->isReg()) in optimizeVCMPSaveExecSequence() 620 MRI->clearKillFlags(Src1->getReg()); in optimizeVCMPSaveExecSequence() 687 if (Src1->isReg() && TRI->isSGPRReg(*MRI, Src1->getReg()) && in tryRecordVCmpxAndSaveexecSequence() 688 MI.modifiesRegister(Src1->getReg(), TRI)) in tryRecordVCmpxAndSaveexecSequence() 712 if (Src1->isReg()) in tryRecordVCmpxAndSaveexecSequence() [all …]
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H A D | SIShrinkInstructions.cpp | 227 MachineOperand &Src1 = MI.getOperand(1); in shrinkScalarCompare() local 228 if (!Src1.isImm()) in shrinkScalarCompare() 243 Src1.setImm(SignExtend32(Src1.getImm(), 32)); in shrinkScalarCompare() 257 Src1.setImm(SignExtend64(Src1.getImm(), 32)); in shrinkScalarCompare() 407 if (Src1.isReg() && TRI->isVGPR(*MRI, Src1.getReg())) in shrinkMadFma() 436 if (Src1.isImm() && !TII->isInlineConstant(Src1)) in shrinkMadFma() 473 .add(Src1) in shrinkMadFma() 495 MachineOperand *SrcImm = Src1; in shrinkScalarLogicOp() 830 std::swap(Src0, Src1); in runOnMachineFunction() 843 if (Src1->isImm() && isKImmOperand(*Src1)) { in runOnMachineFunction() [all …]
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H A D | GCNDPPCombine.cpp | 313 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst() local 314 if (Src1) { in createDPPInst() 325 if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) { in createDPPInst() 330 DPPInst.add(*Src1); in createDPPInst() 486 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst() local 487 if (!Src1 || !Src1->isReg()) { in createDPPInst() 495 CombOldVGPR = getRegSubRegPair(*Src1); in createDPPInst() 689 if ((Use == Src0 && ((Src1 && Src1->isIdenticalTo(*Src0)) || in combineDPPMov() 691 (Use == Src1 && (Src1->isIdenticalTo(*Src0) || in combineDPPMov() 692 (Src2 && Src2->isIdenticalTo(*Src1))))) { in combineDPPMov() [all …]
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H A D | SIPeepholeSDWA.cpp | 549 if (!Src1->isReg() || Src1->getReg().isPhysical() || in matchSDWAOperand() 556 Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD); in matchSDWAOperand() 588 if (!Src1->isReg() || Src1->getReg().isPhysical() || in matchSDWAOperand() 597 Src1, Dst, BYTE_1, false, false, in matchSDWAOperand() 621 auto Offset = foldToImm(*Src1); in matchSDWAOperand() 668 auto ValSrc = Src1; in matchSDWAOperand() 672 Imm = foldToImm(*Src1); in matchSDWAOperand() 969 if (!Src1->isReg() && !Src1->isImm()) in isConvertibleToSDWA() 1026 if (Src1) { in convertToSDWA() 1033 SDWAInst.add(*Src1); in convertToSDWA() [all …]
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H A D | AMDGPURegBankCombiner.cpp | 317 MachineInstr *Src1 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI); in matchFPMed3ToClamp() local 320 if (isFCst(Src0) && !isFCst(Src1)) in matchFPMed3ToClamp() 321 std::swap(Src0, Src1); in matchFPMed3ToClamp() 322 if (isFCst(Src1) && !isFCst(Src2)) in matchFPMed3ToClamp() 323 std::swap(Src1, Src2); in matchFPMed3ToClamp() 324 if (isFCst(Src0) && !isFCst(Src1)) in matchFPMed3ToClamp() 325 std::swap(Src0, Src1); in matchFPMed3ToClamp() 326 if (!isClampZeroToOne(Src1, Src2)) in matchFPMed3ToClamp()
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H A D | AMDGPUCombinerHelper.h | 31 Register Src1, Register Src2); 33 Register Src1, Register Src2);
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H A D | AMDGPUCombinerHelper.cpp | 420 Register Src1, in matchExpandPromotedF16FMed3() argument 427 return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) && in matchExpandPromotedF16FMed3() 433 Register Src1, in applyExpandPromotedF16FMed3() argument 440 Src1 = Builder.buildFPTrunc(LLT::scalar(16), Src1).getReg(0); in applyExpandPromotedF16FMed3() 444 auto A1 = Builder.buildFMinNumIEEE(Ty, Src0, Src1); in applyExpandPromotedF16FMed3() 445 auto B1 = Builder.buildFMaxNumIEEE(Ty, Src0, Src1); in applyExpandPromotedF16FMed3()
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H A D | SIFoldOperands.cpp | 1215 if (!Src0->isImm() && !Src1->isImm()) in tryConstantFoldOp() 1221 if (Src0->isImm() && Src1->isImm()) { in tryConstantFoldOp() 1239 if (Src0->isImm() && !Src1->isImm()) { in tryConstantFoldOp() 1240 std::swap(Src0, Src1); in tryConstantFoldOp() 1300 if (!Src1->isIdenticalTo(*Src0)) { in tryFoldCndMask() 1510 if (!Src0->isReg() || !Src1->isReg() || in isClamp() 1511 Src0->getReg() != Src1->getReg() || in isClamp() 1644 RegOp = Src1; in isOMod() 1645 } else if (Src1->isImm()) { in isOMod() 1646 ImmOp = Src1; in isOMod() [all …]
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H A D | SIInstrInfo.cpp | 3477 (Src1->isReg() && Src1->getReg() == Reg)) { in FoldImmediate() 3479 Src1->isReg() && Src1->getReg() == Reg ? Src0 : Src1; in FoldImmediate() 4315 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg())) in canShrink() 4339 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) || in canShrink() 4395 if (Src1) in buildShrunkInst() 5761 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2() 5775 if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg())) in legalizeOperandsVOP2() 5817 if ((!Src1.isImm() && !Src1.isReg()) || in legalizeOperandsVOP2() 7611 .add(Src1); in splitScalarNotBinop() 7639 .add(Src1); in splitScalarBinOpN2() [all …]
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H A D | SIFixSGPRCopies.cpp | 711 MachineOperand &Src1 = MI.getOperand(Src1Idx); in runOnMachineFunction() local 716 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) && in runOnMachineFunction() 717 Src1.getReg() != AMDGPU::M0)) { in runOnMachineFunction() 724 for (MachineOperand *MO : {&Src0, &Src1}) { in runOnMachineFunction() 749 .add(Src1); in runOnMachineFunction() 750 Src1.ChangeToRegister(AMDGPU::M0, false); in runOnMachineFunction()
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H A D | AMDGPUPostLegalizerCombiner.cpp | 441 Register Src1 = MI.getOperand(2).getReg(); in matchCombine_s_mul_u64() local 445 if (KB->getKnownBits(Src1).countMinLeadingZeros() >= 32 && in matchCombine_s_mul_u64() 451 if (KB->computeNumSignBits(Src1) >= 33 && in matchCombine_s_mul_u64()
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H A D | SILoadStoreOptimizer.cpp | 1581 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair() local 1586 .add(*Src1) in mergeTBufferStorePair() 1679 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeFlatStorePair() local 1684 .add(*Src1) in mergeFlatStorePair() 1915 .add(*Src1) in mergeBufferStorePair() 2082 BaseLo = *Src1; in processBaseWithConstOffset() 2084 if (!(Offset0P = extractConstOffset(*Src1))) in processBaseWithConstOffset() 2090 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); in processBaseWithConstOffset() 2093 std::swap(Src0, Src1); in processBaseWithConstOffset() 2095 if (!Src1->isImm()) in processBaseWithConstOffset() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenMux.cpp | 134 unsigned getMuxOpcode(const MachineOperand &Src1, 205 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, in getMuxOpcode() argument 207 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode() 299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local 300 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); in genMuxInBlock() 317 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock() 318 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
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H A D | HexagonPeephole.cpp | 151 MachineOperand &Src1 = MI.getOperand(1); in runOnMachineFunction() local 153 if (Src1.getImm() != 0) in runOnMachineFunction() 168 MachineOperand &Src1 = MI.getOperand(1); in runOnMachineFunction() local 173 Register SrcReg = Src1.getReg(); in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 299 unsigned Src1 = 0, SubReg1; in transformInstruction() local 328 Src1 = MOSrc1->getReg(); in transformInstruction() 347 if (!Src1) { in transformInstruction() 349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction() 350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction() 364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCExpandAtomicPseudoInsts.cpp | 54 Register Src1) { in PairedCopy() argument 57 if (Dest0 == Src1 && Dest1 == Src0) { in PairedCopy() 62 } else if (Dest0 != Src0 || Dest1 != Src1) { in PairedCopy() 63 if (Dest0 == Src1 || Dest1 != Src0) { in PairedCopy() 64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy() 68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 173 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForMemcmp() argument 181 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes); in EmitTargetCodeForMemcmp() 183 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size); in EmitTargetCodeForMemcmp() 225 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForStrcmp() argument 228 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other); in EmitTargetCodeForStrcmp() 230 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1, in EmitTargetCodeForStrcmp()
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H A D | SystemZSelectionDAGInfo.h | 39 SDValue Src1, SDValue Src2, SDValue Size, 55 SDValue Src1, SDValue Src2,
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/freebsd/sys/contrib/edk2/Include/Protocol/ |
H A D | DevicePathUtilities.h | 68 IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1,
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