Searched refs:Src1RC (Results 1 – 5 of 5) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.td | 1711 Src1Mod:$src1_modifiers, Src1RC:$src1, 1714 Src1Mod:$src1_modifiers, Src1RC:$src1, 1720 (ins Src0RC:$src0, Src1RC:$src1)) 1729 Src1Mod:$src1_modifiers, Src1RC:$src1, 1734 Src1Mod:$src1_modifiers, Src1RC:$src1, 1738 Src1Mod:$src1_modifiers, Src1RC:$src1, 1743 Src1Mod:$src1_modifiers, Src1RC:$src1, 1747 Src1Mod:$src1_modifiers, Src1RC:$src1, 1790 dag ret = getInsVOP3Base<Src0RC, Src1RC, 1819 (ins Src0RC:$src0, Src1RC:$src1) [all …]
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H A D | VOP1Instructions.td | 385 class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> { 390 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0); 391 let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
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H A D | SIInstrInfo.cpp | 7730 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalarSMulU64() local 7736 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulU64() 7745 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in splitScalarSMulU64() 7749 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in splitScalarSMulU64() 7839 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalarSMulPseudo() local 7845 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalarSMulPseudo() 7854 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in splitScalarSMulPseudo() 7905 const TargetRegisterClass *Src1RC = Src1.isReg() ? in splitScalar64BitBinaryOp() local 7910 RI.getSubRegisterClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() 7914 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp() [all …]
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H A D | AMDGPUInstructionSelector.cpp | 831 const TargetRegisterClass *Src1RC = in selectG_INSERT() local 837 if (!Src0RC || !Src1RC) in selectG_INSERT() 842 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) in selectG_INSERT()
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H A D | SIISelLowering.cpp | 4831 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter() local 4838 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter() 4843 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter() 4848 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter() 5060 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter() local 5067 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter() 5072 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter() 5077 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
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