| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 405 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); in lowerInlineAsm() local
406 assert(SrcRegs.size() == 1 && "Single register is expected here"); in lowerInlineAsm()
409 Register In = SrcRegs[0]; in lowerInlineAsm()
413 if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder)) in lowerInlineAsm()
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| H A D | CallLowering.cpp | 298 ArrayRef<Register> SrcRegs) { in mergeVectorRegsToResultRegs() argument
301 LLT PartLLT = MRI.getType(SrcRegs[0]); in mergeVectorRegsToResultRegs()
308 return B.buildConcatVectors(DstRegs[0], SrcRegs); in mergeVectorRegsToResultRegs()
317 DstRegs[0], B.buildMergeLikeInstr(LCMTy, SrcRegs)); in mergeVectorRegsToResultRegs()
321 assert(SrcRegs.size() == 1); in mergeVectorRegsToResultRegs()
322 UnmergeSrcReg = SrcRegs[0]; in mergeVectorRegsToResultRegs()
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| H A D | LegalizerHelper.cpp | 1597 SmallVector<Register, 2> SrcRegs; in narrowScalar() local
1603 SrcRegs.push_back(SrcReg); in narrowScalar()
1618 DstRegs.push_back(SrcRegs[i]); in narrowScalar()
3014 SmallVector<Register, 8> SrcRegs; in lowerBitcast() local
3052 for (Register &SrcReg : SrcRegs) in lowerBitcast()
3063 SmallVector<Register, 8> SrcRegs; in lowerBitcast() local
5702 DstRegs.push_back(SrcRegs[i]); in narrowScalarExtract()
5718 Register SegReg = SrcRegs[i]; in narrowScalarExtract()
5754 SrcRegs.push_back(Reg); in narrowScalarInsert()
5770 Register SrcReg = SrcRegs[I]; in narrowScalarInsert()
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| H A D | IRTranslator.cpp | 1483 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateExtractValue() local
1489 DstRegs[i] = SrcRegs[Idx++]; in translateExtractValue()
1500 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateInsertValue() local
1508 DstRegs[i] = SrcRegs[i]; in translateInsertValue()
1692 SmallVector<Register, 3> SrcRegs; in translateMemFunc() local
1700 SrcRegs.push_back(SrcReg); in translateMemFunc()
1706 Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1]; in translateMemFunc()
1711 for (Register SrcReg : SrcRegs) in translateMemFunc()
3138 const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0)); in translateFreeze() local
3140 assert(DstRegs.size() == SrcRegs.size() && in translateFreeze()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 1111 Register SrcRegs[] = {0, 0}; in LowerPATCHABLE_EVENT_CALL() local
1121 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_EVENT_CALL()
1122 assert(SrcRegs[I].isValid() && "Invalid operand"); in LowerPATCHABLE_EVENT_CALL()
1123 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_EVENT_CALL()
1137 if (SrcRegs[I] != DestRegs[I]) in LowerPATCHABLE_EVENT_CALL()
1139 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1210 Register SrcRegs[] = {0, 0, 0}; in LowerPATCHABLE_TYPED_EVENT_CALL() local
1220 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_TYPED_EVENT_CALL()
1221 assert(SrcRegs[I].isValid() && "Invalid operand"); in LowerPATCHABLE_TYPED_EVENT_CALL()
1222 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_TYPED_EVENT_CALL()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 820 const SmallVectorImpl<RegSubRegPair> &SrcRegs, in insertPHI() argument
822 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?"); in insertPHI()
824 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
827 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
834 for (const RegSubRegPair &RegPair : SrcRegs) { in insertPHI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 987 SmallSet<std::pair<Register, unsigned>, 4> SrcRegs; in needToBeConvertedToVALU() local
996 SrcRegs.insert(std::pair(SiblingCopy->getOperand(1).getReg(), in needToBeConvertedToVALU()
1000 Info->SiblingPenalty = SrcRegs.size(); in needToBeConvertedToVALU()
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| H A D | AMDGPURegisterBankInfo.cpp | 1140 SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingLoad() local
1142 if (SrcRegs.empty()) in applyMappingLoad()
1143 SrcRegs.push_back(MI.getOperand(1).getReg()); in applyMappingLoad()
1149 Register BasePtrReg = SrcRegs[0]; in applyMappingLoad()
2609 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
2610 if (SrcRegs.empty()) in applyMappingImpl()
2627 B.buildFreeze(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2629 auto Freeze = B.buildFreeze(S32, SrcRegs[0]); in applyMappingImpl()
2638 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2691 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
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| H A D | AMDGPULegalizerInfo.cpp | 2702 SmallVector<Register, 8> SrcRegs; in legalizeInsertVectorElt() local
2704 SrcRegs.push_back(MRI.createGenericVirtualRegister(EltTy)); in legalizeInsertVectorElt()
2705 B.buildUnmerge(SrcRegs, Vec); in legalizeInsertVectorElt()
2707 SrcRegs[IdxVal] = MI.getOperand(2).getReg(); in legalizeInsertVectorElt()
2708 B.buildMergeLikeInstr(Dst, SrcRegs); in legalizeInsertVectorElt()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 313 SmallVector<Register, 8> SrcRegs(NumSrcs); in tryCombineTrunc()
315 SrcRegs[i] = SrcMerge->getSourceReg(i); in tryCombineTrunc()
317 Builder.buildMergeValues(DstReg, SrcRegs); in tryCombineTrunc()
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