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Searched refs:TargetSchedModel (Results 1 – 25 of 42) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp43 bool TargetSchedModel::hasInstrSchedModel() const { in hasInstrSchedModel()
47 bool TargetSchedModel::hasInstrItineraries() const { in hasInstrItineraries()
51 void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo) { in init()
73 bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI, in mustBeginGroup()
84 bool TargetSchedModel::mustEndGroup(const MachineInstr *MI, in mustEndGroup()
95 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI, in getNumMicroOps()
120 const MCSchedClassDesc *TargetSchedModel::
173 unsigned TargetSchedModel::computeOperandLatency( in computeOperandLatency()
257 TargetSchedModel::computeInstrLatency(const MachineInstr *MI, in computeInstrLatency()
273 unsigned TargetSchedModel::
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H A DMachineTraceMetrics.cpp125 for (TargetSchedModel::ProcResIter in getResources()
907 const TargetSchedModel &SchedModel, in updatePhysDepsUpwards()
964 const TargetSchedModel &SchedModel, in pushDepHeight()
1245 for (TargetSchedModel::ProcResIter in getResourceLength()
H A DMachineScheduler.cpp980 for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), in dumpScheduleTraceTopDown()
1062 for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), in dumpScheduleTraceBottomUp()
2241 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { in init()
2250 for (TargetSchedModel::ProcResIter in init()
2263 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) { in init()
2702 for (TargetSchedModel::ProcResIter in bumpNode()
2716 for (TargetSchedModel::ProcResIter in bumpNode()
2933 const TargetSchedModel *SchedModel) { in initResourceDelta()
2938 for (TargetSchedModel::ProcResIter in initResourceDelta()
H A DVLIWMachineScheduler.cpp66 const TargetSchedModel *SM) in VLIWResourceModel()
306 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in createVLIWResourceModel()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DVLIWMachineScheduler.h40 const TargetSchedModel *SchedModel;
50 VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM);
129 const TargetSchedModel *SchedModel = nullptr;
158 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) { in init()
212 const TargetSchedModel *SchedModel = nullptr;
246 const TargetSchedModel *SchedModel) const;
H A DTargetSchedule.h30 class TargetSchedModel {
49 TargetSchedModel() : SchedModel(MCSchedModel::Default) {} in TargetSchedModel() function
H A DTargetSubtargetInfo.h54 class TargetSchedModel; variable
146 const TargetSchedModel *SchedModel) const { in resolveSchedClass()
H A DMachineScheduler.h611 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
842 const TargetSchedModel *SchedModel = nullptr;
953 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
1162 const TargetSchedModel *SchedModel);
1167 const TargetSchedModel *SchedModel = nullptr;
H A DScheduleDAGInstrs.h127 TargetSchedModel SchedModel;
264 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel()
H A DMachineTraceMetrics.h102 TargetSchedModel SchedModel;
H A DTargetInstrInfo.h62 class TargetSchedModel; variable
1774 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, in hasHighOperandLatency()
1784 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.h48 const TargetSchedModel *SchedModel;
111 const TargetSchedModel *SM) in SystemZHazardRecognizer()
H A DSystemZHazardRecognizer.cpp175 for (TargetSchedModel::ProcResIter in dumpSU()
296 for (TargetSchedModel::ProcResIter in EmitInstruction()
400 for (TargetSchedModel::ProcResIter in resourcesCost()
H A DSystemZMachineScheduler.h38 TargetSchedModel SchedModel;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h35 const TargetSchedModel *SchedModel) const override;
H A DHexagonMachineScheduler.cpp41 const TargetSubtargetInfo &STI, const TargetSchedModel *SchedModel) const { in createVLIWResourceModel()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp35 TargetSchedModel SchedModel;
H A DAArch64Schedule.td10 // const MachineInstr *MI and const TargetSchedModel *SchedModel
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h49 TargetSchedModel TSchedModel;
H A DGCNSchedStrategy.h304 const TargetSchedModel &SM);
H A DAMDGPUInsertDelayAlu.cpp33 TargetSchedModel SchedModel;
H A DGCNSchedStrategy.cpp998 const TargetSchedModel &SM) { in computeSUnitReadyCycle()
1046 const TargetSchedModel &SM = ST.getInstrInfo()->getSchedModel(); in getScheduleMetrics()
1079 const TargetSchedModel &SM = ST.getInstrInfo()->getSchedModel(); in getScheduleMetrics()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp93 TargetSchedModel TSM;
H A DX86InstrInfo.h533 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h464 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
469 bool hasLowDefLatency(const TargetSchedModel &SchedModel,

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