Searched refs:TruncMask (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVELaneInterleavingPass.cpp | 345 SmallVector<int, 16> TruncMask; in tryInterleave() local
356 TruncMask.push_back(Base + i); in tryInterleave()
357 TruncMask.push_back(Base + i + BaseElts / 2); in tryInterleave()
386 Value *Shuf = Builder.CreateShuffleVector(I, TruncMask); in tryInterleave()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCodeGenPrepare.cpp | 1311 ConstantInt *TruncMask in expandDivRem24Impl() local
1313 Res = Builder.CreateAnd(Res, TruncMask); in expandDivRem24Impl()
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| H A D | AMDGPUISelLowering.cpp | 1971 SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT); in LowerDIVREM24() local
1972 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask); in LowerDIVREM24()
1973 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask); in LowerDIVREM24()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2538 APInt TruncMask = DemandedBits.zext(OperandBitWidth); in SimplifyDemandedBits() local
2539 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, Known, TLO, in SimplifyDemandedBits()
2546 Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1)) in SimplifyDemandedBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 16376 uint64_t TruncMask = ShiftLHS.getConstantOperandVal(1); in isDesirableToCommuteWithShift() local
16377 if (isMask_64(TruncMask)) { in isDesirableToCommuteWithShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41726 APInt TruncMask = OriginalDemandedBits.zext(SrcVT.getScalarSizeInBits()); in SimplifyDemandedBitsForTargetNode() local
41728 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, KnownOp, TLO, Depth + 1)) in SimplifyDemandedBitsForTargetNode()
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