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Searched refs:UINT_TO_FP (Results 1 – 25 of 39) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2219 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
2220 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
2338 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
2339 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
2340 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, in getCastInstrCost()
2341 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, in getCastInstrCost()
2342 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
2343 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, in getCastInstrCost()
2344 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
2345 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp685 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
771 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
773 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
775 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
777 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
779 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
781 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
783 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
785 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
787 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp175 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
180 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addTypeForNEON()
306 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
459 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
470 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand); in addMVEVectorTypes()
947 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
948 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
1072 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
5990 case ISD::UINT_TO_FP: in LowerVectorINT_TO_FP()
5992 Opc = ISD::UINT_TO_FP; in LowerVectorINT_TO_FP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2336 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
2337 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
2338 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
2344 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
2345 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
2346 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
2351 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
2352 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
2358 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
2368 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp538 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
539 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
540 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
988 ISD::UINT_TO_FP}); in AArch64TargetLowering()
1121 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom); in AArch64TargetLowering()
1302 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1400 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1922 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForFixedLengthSVE()
6254 case ISD::UINT_TO_FP: in LowerOperation()
17410 (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP)) in performFDivCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def59 DAG_INSTRUCTION(UIToFP, 1, 1, experimental_constrained_uitofp, UINT_TO_FP)
H A DVPIntrinsics.def464 HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UINT_TO_FP, UIToFP, UINT_TO_FP, 1)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h791 UINT_TO_FP, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp175 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
261 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
1980 case ISD::UINT_TO_FP: in LowerConvertLow()
2491 assert(N->getOpcode() == ISD::UINT_TO_FP || in performVectorExtendToFPCombine()
2505 N->getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in performVectorExtendToFPCombine()
2877 case ISD::UINT_TO_FP: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp255 setOperationAction(ISD::UINT_TO_FP, T, Custom); in initializeHVXLowering()
328 setOperationAction(ISD::UINT_TO_FP, T, Custom); in initializeHVXLowering()
429 setOperationAction(ISD::UINT_TO_FP, VecTy, Custom); in initializeHVXLowering()
2303 Op.getOpcode() == ISD::UINT_TO_FP); in LowerHvxIntToFp()
2677 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in EqualizeFpIntConversion()
2828 assert(Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in ExpandHvxIntToFp()
3155 case ISD::UINT_TO_FP: in LowerHvxOperation()
3237 case ISD::UINT_TO_FP: return LowerHvxIntToFp(Op, DAG); in LowerHvxOperation()
3404 case ISD::UINT_TO_FP: in LowerHvxOperationWrapper()
H A DHexagonISelLowering.cpp1778 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1779 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1780 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp459 case ISD::UINT_TO_FP: in LegalizeOp()
687 case ISD::UINT_TO_FP: in Promote()
793 unsigned Opc = (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteINT_TO_FP()
943 case ISD::UINT_TO_FP: in Expand()
H A DSelectionDAGDumper.cpp367 case ISD::UINT_TO_FP: return "uint_to_fp"; in getOperationName()
H A DLegalizeFloatTypes.cpp145 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break; in SoftenFloatResult()
1362 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break; in ExpandFloatResult()
2450 case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break; in PromoteFloatResult()
2855 case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break; in SoftPromoteHalfResult()
H A DLegalizeDAG.cpp1026 case ISD::UINT_TO_FP: in LegalizeOp()
2846 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP; in PromoteLegalINT_TO_FP()
3326 case ISD::UINT_TO_FP: in ExpandNode()
4663 case ISD::UINT_TO_FP: { in ConvertNodeToLibcall()
4937 if (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteNode()
5012 case ISD::UINT_TO_FP: in PromoteNode()
H A DLegalizeVectorTypes.cpp114 case ISD::UINT_TO_FP: in ScalarizeVectorResult()
685 case ISD::UINT_TO_FP: in ScalarizeVectorOperand()
1118 case ISD::UINT_TO_FP: in SplitVectorResult()
3013 case ISD::UINT_TO_FP: in SplitVectorOperand()
4252 case ISD::UINT_TO_FP: in WidenVectorResult()
6078 case ISD::UINT_TO_FP: in WidenVectorOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp438 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
463 ISD::UINT_TO_FP, ISD::SDIV, ISD::UDIV, in AMDGPUTargetLowering()
1360 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
1887 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2029 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo); in LowerUDIVREM64()
2030 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi); in LowerUDIVREM64()
3252 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
3289 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
3292 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
3314 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
[all …]
H A DR600ISelLowering.cpp1727 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1728 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp264 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
284 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
533 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
547 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
1393 setTargetDAGCombine(ISD::UINT_TO_FP); in PPCTargetLowering()
8509 UI->getOpcode() != ISD::UINT_TO_FP && in directMoveIsProfitable()
11647 case ISD::UINT_TO_FP: in LowerOperation()
14865 FirstInput.getOpcode() != ISD::UINT_TO_FP) in DAGCombineBuildVector()
14868 N->getOperand(1).getOpcode() != ISD::UINT_TO_FP) in DAGCombineBuildVector()
14907 N->getOpcode() == ISD::UINT_TO_FP) && in combineFPToIntToFP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp273 setOperationAction(ISD::UINT_TO_FP, MVT::i128, LibCall); in SystemZTargetLowering()
315 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); in SystemZTargetLowering()
316 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in SystemZTargetLowering()
462 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
463 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
482 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
483 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
714 ISD::UINT_TO_FP, in SystemZTargetLowering()
7320 (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND); in combineINT_TO_FP()
7685 case ISD::UINT_TO_FP: return combineINT_TO_FP(N, DCI); in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp119 setOperationAction(ISD::UINT_TO_FP, GRLenVT, Expand); in LoongArchTargetLowering()
194 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in LoongArchTargetLowering()
269 setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal); in LoongArchTargetLowering()
315 setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal); in LoongArchTargetLowering()
403 case ISD::UINT_TO_FP: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1696 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1698 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3267 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3638 case ISD::UINT_TO_FP: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp214 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64 in initSPUActions()
216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in initSPUActions()
2915 case ISD::UINT_TO_FP: in isI32Insn()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp888 case ISD::UINT_TO_FP: in getCastInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp530 ISD::UDIV, ISD::UDIVREM, ISD::UINT_TO_FP, ISD::UMAX, in NVPTXTargetLowering()
698 ISD::SINT_TO_FP, ISD::UINT_TO_FP}, in NVPTXTargetLowering()
781 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
2712 case ISD::UINT_TO_FP: in LowerOperation()

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