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Searched refs:VRC (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp60 VRC = RC; in Initialize()
163 VRC, MRI, TII); in GetValueInMiddleOfBlock()
201 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
305 Updater->VRC, Updater->MRI, in GetUndefVal()
316 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td559 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
561 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
571 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
666 (ins VRC:$vy, VRC:$vz, VRC:$vw)>;
669 (ins VRC:$vy, RC:$sy, VRC:$vw)>;
672 (ins VRC:$vy, SIMM:$sy, VRC:$vw)>;
675 (ins RC:$sy, VRC:$vz, VRC:$vw)>;
678 (ins SIMM:$sy, VRC:$vz, VRC:$vw)>;
715 defm vr : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, RC:$sy)>;
726 (ins VRC:$vy, VRC:$vz, RC:$sy)>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/toshiba/
H A Dtmpv7708-visrobo-vrc.dtsi3 * Device Tree File for TMPV7708 VisROBO VRC SoM
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineSSAUpdater.h44 const TargetRegisterClass *VRC = nullptr; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h259 getEquivalentSGPRClass(const TargetRegisterClass *VRC) const;
H A DSIInstrInfo.cpp5518 Register Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
5948 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()
5949 VRC = RI.getEquivalentVGPRClass(VRC); in readlaneVGPRToSGPR()
6474 VRC = OpRC; in legalizeOperands()
6484 if (!VRC) { in legalizeOperands()
6487 VRC = &AMDGPU::VReg_1RegClass; in legalizeOperands()
6493 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6494 ? RI.getEquivalentAGPRClass(VRC) in legalizeOperands()
6495 : RI.getEquivalentVGPRClass(VRC); in legalizeOperands()
6497 RC = VRC; in legalizeOperands()
[all …]
H A DSIRegisterInfo.cpp2874 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in getEquivalentVGPRClass() local
2875 assert(VRC && "Invalid register class size"); in getEquivalentVGPRClass()
2876 return VRC; in getEquivalentVGPRClass()
2888 SIRegisterInfo::getEquivalentSGPRClass(const TargetRegisterClass *VRC) const { in getEquivalentSGPRClass()
2889 unsigned Size = getRegSizeInBits(*VRC); in getEquivalentSGPRClass()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local
452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
456 if (RC && RC != VRC) in ConstrainForSubReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td311 class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
313 width.Value{2-0}, (outs VRC:$vd), (ins GPRMemZeroOffset:$rs1),
382 class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC>
384 0b000, (outs), (ins VRC:$vs3, GPRMemZeroOffset:$rs1),
1021 multiclass VWholeLoadN<int l, bits<3> nf, string opcodestr, RegisterClass VRC> {
1025 def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,
/freebsd/share/misc/
H A Dusb_vendors8272 9881 IR receiver [VRC-1100 Vista MCE Remote Control]
22598 2012 Virtual Reality Controller [VRC]