| /freebsd/contrib/llvm-project/clang/lib/Headers/ |
| H A D | hvx_hexagon_protos.h | 283 #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) argument
327 #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) argument
393 #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) argument
470 #define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) argument
558 #define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) argument
624 #define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) argument
657 #define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) argument
822 #define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) argument
888 #define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) argument
2428 #define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatternsV65.td | 14 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
24 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
34 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
49 RC1:$Vv),
60 RC1:$Vv),
71 RC1:$Vv),
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| H A D | HexagonPatternsHVX.td | 674 // Do it as (Vu << Vs) | (Vv >> (BW-Vs)).
686 // Vx[1]:Vx[0] = V6_vasr_into Vx[0], Vv, Vs
705 $Vv,
710 $Vv,
715 // Do it as (Vu >> -(BW-Vs)) | (Vv >> Vs).
719 (V6_vlsrhv $Vv, $Vs))>;
722 (V6_vlsrwv $Vv, $Vs))>;
726 // Vx[1]:Vx[0] = V6_vasr_into Vx[0], Vv, Vs
916 def: Pat<(VecI8 (mulhs HVI8:$Vu, HVI8:$Vv)),
919 def: Pat<(VecI16 (mulhs HVI16:$Vu, HVI16:$Vv)),
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| H A D | HexagonISelDAGToDAGHVX.cpp | 819 std::copy(Vv.begin(), Vv.end(), Vdd.begin()); in vshuffvdd()
839 std::copy(Vv.begin(), Vv.end(), Vdd.begin()); in vdealvdd()
863 Vd[i * Size + b] = Vv[(2 * i + Odd) * Size + b]; in vpack()
886 MaskT T = vdealvdd(Vu, Vv, Len - 2 * Size); in vdeal()
890 MaskT vdealb4w(ArrayRef<int> Vu, ArrayRef<int> Vv) { in vdealb4w() argument
894 Vd[0 * (Len / 4) + i] = Vv[4 * i + 0]; in vdealb4w()
895 Vd[1 * (Len / 4) + i] = Vv[4 * i + 2]; in vdealb4w()
904 MaskT Vu(Length), Vv(Length); in mask() local
906 std::iota(Vv.begin(), Vv.end(), 0); // Low in mask()
907 return S(Vu, Vv, args...); in mask()
[all …]
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| H A D | HexagonISelLoweringHVX.cpp | 1926 SDValue Vv = Op.getOperand(1); in LowerHvxMulLoHi() local
1932 SDValue Lo = DAG.getNode(ISD::MUL, dl, ty(Op), {Vu, Vv}); in LowerHvxMulLoHi()
1942 return emitHvxMulLoHiV62(Vu, SignedVu, Vv, SignedVv, dl, DAG); in LowerHvxMulLoHi()
1948 SDValue Hi = emitHvxMulHsV60(Vu, Vv, dl, DAG); in LowerHvxMulLoHi()
1954 return emitHvxMulLoHiV60(Vu, SignedVu, Vv, SignedVv, dl, DAG); in LowerHvxMulLoHi()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsHexagon.td | 390 // V6_vmpyss_parts(Vu,Vv) = (MulHS(Vu,Vv), Mul(Vu,Vv))
391 // V6_vmpyuu_parts(Vu,Vv) = (MulHU(Vu,Vv), Mul(Vu,Vv))
392 // V6_vmpyus_parts(Vu,Vv) = (MulHUS(Vu,Vv), Mul(Vu,Vv))
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedExynosM4.td | 742 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
748 def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
793 def : InstRW<[M4WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
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| H A D | AArch64SchedExynosM5.td | 790 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
796 def : InstRW<[M5WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
835 def : InstRW<[M5WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
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| H A D | AArch64SchedExynosM3.td | 624 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>;
654 def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
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| H A D | AArch64SchedA55.td | 431 def : InstRW<[CortexA55WriteAluVq_4], (instregex "[SU](MAX|MIN)Vv")>;
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| H A D | AArch64SchedTSV110.td | 660 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^F(MAX|MIN)(NM)?Vv")>;
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| H A D | AArch64SchedA57.td | 491 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
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| H A D | AArch64SchedAmpere1.td | 910 def : InstRW<[Ampere1Write_10cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv.[if](32|64)")>;
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| H A D | AArch64SchedAmpere1B.td | 890 def : InstRW<[Ampere1BWrite_6cyc_2XY], (instregex "^F(MAX|MIN)(NM)?Vv.[if](32|64)")>;
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| H A D | AArch64SchedA510.td | 441 def : InstRW<[CortexA510Write<4, CortexA510UnitVALU>], (instregex "[SU](MAX|MIN)Vv")>;
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| /freebsd/contrib/sendmail/ |
| H A D | PGPKEYS | 4379 /Vv+fl5wdw3YVAgKiQCVAwUQNxJ38gx2JIpOldm1AQEeFgQAmK75xIhzb84Qfh9O
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