/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchLBTInstrFormats.td | 121 : LAInst<(outs), (ins GPR:$rj, uimm6:$imm6), 122 deriveInsnMnemonic<NAME>.ret, "$rj, $imm6"> { 123 bits<6> imm6; 127 let Inst{15-10} = imm6;
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H A D | LoongArchInstrFormats.td | 131 bits<6> imm6; 136 let Inst{15-10} = imm6;
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H A D | LoongArchLASXInstrFormats.td | 233 bits<6> imm6; 238 let Inst{15-10} = imm6;
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H A D | LoongArchLSXInstrFormats.td | 261 bits<6> imm6; 266 let Inst{15-10} = imm6;
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H A D | LoongArchLASXInstrInfo.td | 97 : Fmt2RI6_XXI<op, (outs LASX256:$xd), (ins LASX256:$xj, ImmOpnd:$imm6), 98 "$xd, $xj, $imm6">; 161 : Fmt2RI6_XXI<op, (outs LASX256:$dst), (ins LASX256:$xd, LASX256:$xj, ImmOpnd:$imm6), 162 "$xd, $xj, $imm6">;
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H A D | LoongArchLSXInstrInfo.td | 233 : Fmt2RI6_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm6), 234 "$vd, $vj, $imm6">; 296 : Fmt2RI6_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm6), 297 "$vd, $vj, $imm6">;
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H A D | LoongArchInstrInfo.td | 628 : Fmt2RI6<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm6), 629 "$rd, $rj, $imm6">;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrFormatsC.td | 247 bits<6> imm6; 251 let Inst{12} = imm6{5}; 253 let Inst{6-2} = imm6{4-0}; 280 bits<6> imm6; 284 let Inst{12-7} = imm6;
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H A D | RISCVInstrInfoXCV.td | 293 bits<6> imm6; 297 let Inst{25} = imm6{0}; // funct1 unused 298 let Inst{24-20} = imm6{5-1}; 316 (ins GPR:$rs1, simm6:$imm6), opcodestr, "$rd, $rs1, $imm6">; 320 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, simm6:$imm6), 321 opcodestr, "$rd, $rs1, $imm6"> { 328 (outs GPR:$rd), (ins GPR:$rs1, immtype:$imm6), 329 opcodestr, "$rd, $rs1, $imm6">; 334 (ins GPR:$rd, GPR:$rs1, uimm6:$imm6), 335 opcodestr, "$rd, $rs1, $imm6"> {
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H A D | RISCVInstrInfoC.td | 769 simm6:$imm6), 770 "$opcode, $funct3, $rd, $imm6">; 778 uimm6:$imm6), 779 "$opcode, $funct3, $rs2, $imm6">; 814 def : InstAlias<".insn_ci $opcode, $funct3, $rd, $imm6", 816 simm6:$imm6)>; 820 def : InstAlias<".insn_css $opcode, $funct3, $rs2, $imm6", 822 uimm6:$imm6)>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
H A D | XtensaInstrFormats.td | 202 bits<6> imm6; 205 let Inst{15-12} = imm6{3-0}; 209 let Inst{5-4} = imm6{5-4};
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstrNEON.td | 4020 let Inst{21-19} = 0b001; // imm6 = 001xxx 4024 let Inst{21-20} = 0b01; // imm6 = 01xxxx 4028 let Inst{21} = 0b1; // imm6 = 1xxxxx 4032 // imm6 = xxxxxx 4037 let Inst{21-19} = 0b001; // imm6 = 001xxx 4041 let Inst{21-20} = 0b01; // imm6 = 01xxxx 4045 let Inst{21} = 0b1; // imm6 = 1xxxxx 4049 // imm6 = xxxxxx 4057 let Inst{21-19} = 0b001; // imm6 = 001xxx 4061 let Inst{21-20} = 0b01; // imm6 = 01xxxx [all …]
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H A D | ARMInstrFormats.td | 312 // other shift immediates. The imm6 field is encoded like so: 315 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 316 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 317 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 318 // 64 64 - <imm> is encoded in imm6<5:0>
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H A D | ARMInstrMVE.td | 3893 (outs MQPR:$Qd), (ins MQPR:$Qm, imm_operand_type:$imm6), 3894 "$Qd, $Qm, $imm6", vpred_r, "", !if(fsi, 0b10, 0b01), []> { 3896 bits<6> imm6; 3902 let Inst{19-16} = imm6{3-0}; 3929 let Inst{20} = imm6{4};
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/freebsd/contrib/llvm-project/lld/ELF/Arch/ |
H A D | RISCV.cpp | 369 uint16_t imm6 = extractBits(val, 6, 6) << 7; in relocate() local 373 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | SVEInstrFormats.td | 2849 asm, "\t$Rd, $Rn, $imm6", 2854 bits<6> imm6; 2861 let Inst{10-5} = imm6; 2869 asm, "\t$Rd, $imm6", 2873 bits<6> imm6; 2880 let Inst{10-5} = imm6; 7461 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]", 7467 bits<6> imm6; 7471 let Inst{21-16} = imm6; 7775 bits<6> imm6; [all …]
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H A D | AArch64InstrFormats.td | 1143 // {5-0} - imm6 1173 // {5-0} - imm6 1203 // {5-0} - imm6: #0, #8, #16, or #24 1212 // {5-0} - imm6: #0 or #8 1242 // {5-0} - imm6: #0 or #12 3087 isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4", 3088 (ins GPR64sp:$Rn, uimm6s16:$imm6, imm0_15:$imm4), 3089 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> { 3090 bits<6> imm6; 3094 let Inst{21-16} = imm6;
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H A D | AArch64InstrInfo.td | 2353 def : Pat<(int_aarch64_addg (am_indexedu6s128 GPR64sp:$Rn, uimm6s16:$imm6), imm0_15:$imm4), 2354 (ADDG GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4)>; 2397 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, uimm6s16:$imm6, GPR64sp:$Rm, imm0_15:$imm4), []>,
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 6930 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); in DecodeMVEVCVTt1fp() local 6936 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) in DecodeMVEVCVTt1fp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRInstrInfo.td | 245 // Addressing mode pattern reg+imm6
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
H A D | EmulateInstructionARM.cpp | 2839 uint32_t imm6 = Bits32(opcode, 21, 16); in EmulateB() local 2844 (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); in EmulateB()
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