Searched refs:CHIP_REV_IS_SLOW (Results 1 – 13 of 13) sorted by relevance
288 ((CHIP_REV_IS_SLOW(dev) && (!(dev)->b_is_emul_full)) ? \
256 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) in ecore_is_reg_fifo_empty()279 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) in ecore_wr()303 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) in ecore_rd()
183 if ((CHIP_REV_IS_SLOW(p_hwfn->p_dev) && (size < 16)) ||566 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
741 #define CHIP_REV_IS_SLOW(_p_dev) \ macro751 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
454 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) in ecore_sp_eth_vport_start()603 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { in ecore_sp_update_accept_mode()1353 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { in ecore_filter_ucast_common()
1124 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { in ecore_final_cleanup()1215 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { in ecore_calc_hw_mode()3070 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { in __ecore_hw_set_resc_info()3227 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { in ecore_hw_get_resc()3247 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) && in ecore_hw_get_resc()
2263 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { in ecore_mcp_get_link_state()2494 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) in ecore_mcp_send_drv_version()
3800 u8 offset = (CHIP_REV_IS_SLOW(pdev) ? in ecore_mcast_set_rdata_hdr_e1()4213 if (CHIP_REV_IS_SLOW(pdev)) in ecore_init_mcast_obj()4495 if (!CHIP_REV_IS_SLOW(pdev)) in ecore_init_mac_credit_pool()4507 if (!CHIP_REV_IS_SLOW(pdev)) in ecore_init_mac_credit_pool()4524 if (!CHIP_REV_IS_SLOW(pdev)) in ecore_init_mac_credit_pool()4537 if (!CHIP_REV_IS_SLOW(pdev)) in ecore_init_mac_credit_pool()
61 if (CHIP_REV_IS_SLOW(pdev)) { in lm_mcp_wait_one()
1747 if (CHIP_REV_IS_SLOW(pdev)) in lm_link_on_timer()
2721 if (CHIP_REV_IS_SLOW(pdev)) in init_link_params()3297 if((CHIP_REV_IS_SLOW(pdev) in lm_init_params()
1696 #define CHIP_REV_IS_SLOW(_p) (CHIP_REV(_p) > CHIP_REV_ASIC_MAX) macro1697 …#define CHIP_REV_IS_FPGA(_p) (CHIP_REV_IS_SLOW(_p) && (CHIP_REV(_p) & CHIP_REV_SIM_IS_FPGA))1698 …#define CHIP_REV_IS_EMUL(_p) (CHIP_REV_IS_SLOW(_p) && !(CHIP_REV(_p)& CHIP_REV_SIM_IS_FPGA)…1699 #define CHIP_REV_IS_ASIC(_p) (!CHIP_REV_IS_SLOW(_p))
93 #define CHIP_REV_IS_SLOW(_chip_id) \ macro96 (CHIP_REV_IS_SLOW(_chip_id)&& \99 (CHIP_REV_IS_SLOW(_chip_id)&& \2065 if (CHIP_REV_IS_SLOW(params->chip_id)) { in elink_emac_enable()14145 !CHIP_REV_IS_SLOW(params->chip_id)) { in elink_phy_init()14271 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(params->chip_id))) { in elink_link_reset()14294 if (!CHIP_REV_IS_SLOW(params->chip_id)) in elink_link_reset()