1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H 28 #define _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H 29 30 /* 31 * hci1394_descriptors.h 32 * 1394 Open HCI command descriptors. 33 * These are DMA commands chained together to form packets. 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include <sys/note.h> 41 42 /* 43 * There are 2 different 1394 Open HCI entities defined in this file. 44 * The HCI DMA descriptors (aka context descriptors or descriptor 45 * commands), and the packet formats. 46 * 47 * Packet formats are used within descriptors for transmit and 48 * are available in buffers for receive. EACH PACKET TYPE 49 * (such as read_quadlet_request) may have a different format 50 * depending on whether it is to be transmitted or whether it 51 * is being received. 52 * 53 * In general, fields within a packet remain in the same location 54 * within a quadlet either way. However, the location of the 55 * quadlets themselves may be different. 56 * 57 * In an attempt to clarify what is used for what, Macros used 58 * for setting up packets within a descriptor (an "Immediate" command) 59 * shall have "DESC" in their name. Macros used for reading packets 60 * from an input buffer shall have "PKT" in their name. 61 * 62 * For more information, see OpenHCI 1.00 chapters 7 (Asynch Transmit), 63 * 8 (Asynch Receive), 9 (Isoch Transmit) and 10 (Isoch Receive). 64 * Each chapter shows the DMA descriptors at the beginning, and 65 * the packet formats at the end. 66 * Also see chapter 11 (Self ID). 67 */ 68 69 70 /* 71 * hci1394_desc is the basic format used for the following descriptor commands: 72 * OUTPUT_MORE, OUTPUT_LAST, INPUT_MORE and INPUT_LAST 73 */ 74 typedef struct hci1394_desc_s { 75 uint32_t hdr; 76 uint32_t data_addr; 77 uint32_t branch; /* branch or skip address (& Z) */ 78 uint32_t status; /* status and/or (timestamp or rescount) */ 79 } hci1394_desc_t; 80 81 _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_desc_s)) 82 83 /* 84 * hci1394_desc_imm is the basic format used for the "immediate" descriptor 85 * commands: OUTPUT_MORE_IMMEDIATE and OUTPUT_LAST_IMMEDIATE. 86 */ 87 typedef struct hci1394_desc_imm_s { 88 uint32_t hdr; 89 uint32_t data_addr; 90 uint32_t branch; 91 uint32_t status; 92 uint32_t q1; 93 uint32_t q2; 94 uint32_t q3; 95 uint32_t q4; 96 } hci1394_desc_imm_t; 97 98 _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_desc_imm_s)) 99 100 /* 101 * hci1394_desc_hdr contains the immediate packet header quadlets 102 * for OUTPUT_MORE_IMMEDIATE and OUTPUT_LAST_IMMEDIATE. A packet header 103 * has up to 4 quadlets of data which are specific to the individual operation 104 * and operation type (i.e. this data would be different between a quadlet read 105 * and quadlet write). 106 */ 107 typedef struct hci1394_desc_hdr_s { 108 uint32_t q1; 109 uint32_t q2; 110 uint32_t q3; 111 uint32_t q4; 112 } hci1394_desc_hdr_t; 113 114 115 /* typedefs for each descriptor command */ 116 typedef hci1394_desc_imm_t hci1394_output_more_imm_t; 117 typedef hci1394_desc_t hci1394_output_more_t; 118 typedef hci1394_desc_imm_t hci1394_output_last_imm_t; 119 typedef hci1394_desc_t hci1394_output_last_t; 120 typedef hci1394_desc_t hci1394_input_more_t; 121 typedef hci1394_desc_t hci1394_input_last_t; 122 123 /* 124 * maximum number of 16-byte components comprising a descriptor block. 125 * Note that "immediate" descriptors take up 32-bytes and therefore are 126 * 2 Z counts. Refer to OHCI 1.00 sections 3.1.2, 7.1.5.1, 8.3.1, 9.2.1, 127 * and table 10-2 for context specific info about Z. 128 */ 129 #define HCI1394_DESC_MAX_Z 8 130 131 132 /* 133 * There are two sets of defines below. The first set includes 134 * definitions for the descriptor header. Namely hdr, branch, and stat. 135 * The second set includes definitions for the different packet header 136 * formats that have to be placed in the immediate q1-q4 fields 137 * of a descriptor. 138 */ 139 140 141 /* General descriptor HDR quadlet defs */ 142 #define DESC_HDR_STAT_ENBL 0x08000000 /* AR, IT & IR only */ 143 #define DESC_HDR_STAT_DSABL 0x00000000 /* AR, IT & IR only */ 144 #define DESC_HDR_PING_ENBL 0x00800000 /* AT only */ 145 #define DESC_HDR_REQCOUNT_MASK 0x0000FFFF /* IR only */ 146 #define DESC_HDR_REQCOUNT_SHIFT 0 147 #define DESC_HDR_STVAL_MASK 0x0000FFFF /* IT STORE only */ 148 #define DESC_HDR_STVAL_SHIFT 0 149 #define DESC_GET_HDR_REQCOUNT(DESCP) \ 150 (((DESCP)->hdr & DESC_HDR_REQCOUNT_MASK) >> DESC_HDR_REQCOUNT_SHIFT) 151 152 /* CMD_TYPE values */ 153 #define DESC_TY_OUTPUT_MORE 0x00000000 /* AT & IT */ 154 #define DESC_TY_OUTPUT_LAST 0x10000000 /* AT & IT */ 155 #define DESC_TY_INPUT_MORE 0x20000000 /* AR & IR */ 156 #define DESC_TY_INPUT_LAST 0x30000000 /* IR only */ 157 #define DESC_TY_STORE 0x80000000 /* IT only */ 158 159 /* CMD_KEY values */ 160 #define DESC_KEY_REF 0x00000000 /* reference ptr to data */ 161 #define DESC_KEY_IMMED 0x02000000 /* immediate data */ 162 #define DESC_KEY_STORE 0x06000000 /* store data */ 163 164 /* CMD_BR and CMD_INT values - two bits */ 165 #define DESC_INTR_DSABL 0x00000000 166 #define DESC_INTR_ENBL 0x00300000 167 #define DESC_BR_DSABL 0x00000000 168 #define DESC_BR_ENBL 0x000C0000 169 #define DESC_W_DSABL 0x00000000 170 #define DESC_W_ENBL 0x00030000 171 172 /* 173 * Shortcuts for AT Descriptor types. We will always interrupt upon command 174 * completion for AT OL, OLI, and IM. 175 */ 176 #define DESC_AT_OM DESC_TY_OUTPUT_MORE 177 #define DESC_AT_OMI (DESC_TY_OUTPUT_MORE | DESC_KEY_IMMED) 178 #define DESC_AT_OL (DESC_TY_OUTPUT_LAST | DESC_INTR_ENBL | DESC_BR_ENBL) 179 #define DESC_AT_OLI (DESC_AT_OL | DESC_KEY_IMMED) 180 #define DESC_AR_IM (DESC_TY_INPUT_MORE | DESC_HDR_STAT_ENBL | \ 181 DESC_INTR_ENBL | DESC_BR_ENBL) 182 183 /* 184 * descriptor BRANCH field defs 185 * Branch addresses are 16-byte aligned. the low order 4-bits are 186 * used for the Z value. 187 */ 188 #define DESC_BRANCH_MASK 0xFFFFFFF0 189 #define DESC_Z_MASK 0x0000000F 190 191 #define HCI1394_SET_BRANCH(DESCP, ADDR, Z) ((DESCP)->branch = 0 | \ 192 ((ADDR) & DESC_BRANCH_MASK) | ((Z) & DESC_Z_MASK)) 193 194 #define HCI1394_GET_BRANCH_ADDR(DESCP) ((DESCP)->branch & ~DESC_Z_MASK) 195 #define HCI1394_GET_BRANCH_Z(DESCP) ((DESCP)->branch & DESC_Z_MASK) 196 197 /* 198 * descriptor STATUS field defs. comprised of xfer status and either 199 * a timestamp or a residual count (rescount) 200 */ 201 #define DESC_ST_XFER_STAT_MASK 0xFFFF0000 202 #define DESC_ST_XFER_STAT_SHIFT 16 203 #define DESC_ST_RESCOUNT_MASK 0x0000FFFF /* AR, IR only */ 204 #define DESC_ST_RESCOUNT_SHIFT 0 205 #define DESC_ST_TIMESTAMP_MASK 0x0000FFFF /* AT, IT only */ 206 #define DESC_ST_TIMESTAMP_SHIFT 0 207 208 #define HCI1394_DESC_RESCOUNT_GET(data) ((data) & DESC_ST_RESCOUNT_MASK) 209 #define HCI1394_DESC_TIMESTAMP_GET(data) ((data) & DESC_ST_TIMESTAMP_MASK) 210 211 /* 212 * XFER status fields are the same as the context control fields. 213 * but in the high 16 bits 214 */ 215 #define DESC_XFER_RUN_MASK (OHCI_CC_RUN_MASK << DESC_ST_XFER_STAT_SHIFT) 216 #define DESC_XFER_WAKE_MASK (OHCI_CC_WAKE_MASK << DESC_ST_XFER_STAT_SHIFT) 217 #define DESC_XFER_DEAD_MASK (OHCI_CC_DEAD_MASK << DESC_ST_XFER_STAT_SHIFT) 218 #define DESC_XFER_ACTIVE_MASK (OHCI_CC_ACTIVE_MASK << DESC_ST_XFER_STAT_SHIFT) 219 220 #define DESC_AT_SPD_MASK 0x7 221 #define DESC_AT_SPD_SHIFT 16 222 #define DESC_AR_SPD_MASK 0x00E00000 223 #define DESC_AR_SPD_SHIFT 21 224 #define DESC_AR_EVT_MASK 0x001F0000 225 #define DESC_AR_EVT_SHIFT 16 226 227 #define HCI1394_DESC_EVT_GET(data) \ 228 (((data) & DESC_AR_EVT_MASK) >> DESC_AR_EVT_SHIFT) 229 #define HCI1394_DESC_AR_SPD_GET(data) \ 230 (((data) & DESC_AR_SPD_MASK) >> DESC_AR_SPD_SHIFT) 231 #define HCI1394_DESC_AT_SPD_SET(data) \ 232 (((data) & DESC_AT_SPD_MASK) << DESC_AT_SPD_SHIFT) 233 234 235 /* 236 * XferStatus events are as follows 237 */ 238 #define DESC_EVT_NO_STATUS 0x00 /* AT, AR, IT, IR */ 239 #define DESC_EVT_LONG_PKT 0x02 /* IR */ 240 #define DESC_EVT_MISSING_ACK 0x03 /* AT */ 241 #define DESC_EVT_UNDERRUN 0x04 /* AT, IT */ 242 #define DESC_EVT_OVERRUN 0x05 /* IR */ 243 #define DESC_EVT_DESC_READ 0x06 /* AT, AR, IT, IR */ 244 #define DESC_EVT_DATA_READ 0x07 /* AT, IT */ 245 #define DESC_EVT_DATA_WRITE 0x08 /* AR, IR */ 246 #define DESC_EVT_BUS_RESET 0x09 /* AR */ 247 #define DESC_EVT_TIMEOUT 0x0A /* AT */ 248 #define DESC_EVT_TCODE_ERR 0x0B /* AT, IT */ 249 250 #define DESC_ACK_COMPLETE 0x11 /* AT, AR, IT, IR */ 251 #define DESC_ACK_PENDING 0x12 /* AT, AR */ 252 #define DESC_ACK_BUSY_X 0x14 /* AT */ 253 #define DESC_ACK_BUSY_A 0x15 /* AT */ 254 #define DESC_ACK_BUSY_B 0x16 /* AT */ 255 #define DESC_ACK_TARDY 0x1B /* AT */ 256 #define DESC_ACK_DATA_ERR 0x1D /* AT IR */ 257 #define DESC_ACK_TYPE_ERR 0x1E /* AT, AR */ 258 259 /* 260 * Response packet response codes 261 */ 262 #define DESC_RESP_COMPLETE 0x0 263 #define DESC_RESP_CONFLICT_ERR 0x4 264 #define DESC_RESP_DATA_ERR 0x5 265 #define DESC_RESP_TYPE_ERR 0x6 266 #define DESC_RESP_ADDR_ERR 0x7 267 268 269 /* 270 * Context dependent MACROs used to set up the command headers and 271 * Caller provides only the necessary variables. 272 */ 273 274 /* 275 * Isochronous Transmit Descriptors 276 */ 277 #define HCI1394_INIT_IT_OMORE(DESCP, REQCOUNT) ((DESCP)->hdr = 0 | \ 278 (DESC_TY_OUTPUT_MORE | DESC_KEY_REF | DESC_BR_DSABL | \ 279 ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT))) 280 281 #define HCI1394_INIT_IT_OMORE_IMM(DESCP) ((DESCP)->hdr = 0 | \ 282 (DESC_TY_OUTPUT_MORE | DESC_KEY_IMMED | DESC_BR_DSABL | \ 283 (8 << DESC_HDR_REQCOUNT_SHIFT))) 284 285 #define HCI1394_INIT_IT_OLAST(DESCP, STAT, INTR, REQCOUNT) ((DESCP)->hdr = 0 |\ 286 (DESC_TY_OUTPUT_LAST | (STAT) | DESC_KEY_REF | (INTR) | \ 287 DESC_BR_ENBL | ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT))) 288 289 #define HCI1394_INIT_IT_OLAST_IMM(DESCP, STAT, INTR) ((DESCP)->hdr = 0 | \ 290 (DESC_TY_OUTPUT_LAST | (STAT) | DESC_KEY_IMMED | (INTR) | \ 291 DESC_BR_ENBL | (8 << DESC_HDR_REQCOUNT_SHIFT))) 292 293 #define HCI1394_INIT_IT_STORE(DESCP, VAL) ((DESCP)->hdr = 0 | \ 294 (DESC_TY_STORE | DESC_KEY_STORE | ((VAL) << DESC_HDR_STVAL_SHIFT))) 295 296 /* 297 * Isochronous Receive Descriptors 298 * PPB is Packet-Per-Buffer mode, BF is Buffer-Fill mode 299 */ 300 #define HCI1394_INIT_IR_PPB_IMORE(DESCP, WAIT, REQCOUNT) (DESCP)->hdr = 0 | \ 301 (DESC_TY_INPUT_MORE | DESC_HDR_STAT_DSABL | DESC_KEY_REF | \ 302 DESC_INTR_DSABL | DESC_BR_DSABL | (WAIT) | \ 303 ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 304 (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 305 DESC_ST_RESCOUNT_MASK); 306 307 #define HCI1394_INIT_IR_PPB_ILAST(DESCP, STAT, INTR, WAIT, REQCOUNT) \ 308 (DESCP)->hdr = 0 | (DESC_TY_INPUT_LAST | (STAT) | DESC_KEY_REF | \ 309 (INTR) | DESC_BR_ENBL | (WAIT) | \ 310 ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 311 (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 312 DESC_ST_RESCOUNT_MASK); 313 314 #define HCI1394_INIT_IR_BF_IMORE(DESCP, INT, WAIT, REQCOUNT) \ 315 (DESCP)->hdr = 0 | (DESC_TY_INPUT_MORE | DESC_HDR_STAT_ENBL | \ 316 DESC_KEY_REF | (INT) | DESC_BR_ENBL | (WAIT) | \ 317 ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 318 (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 319 DESC_ST_RESCOUNT_MASK); 320 321 /* 322 * Packet Formats 323 * 324 * HCI packet formats typically comprise 2-4 quadlets for transmit 325 * and 3-5 quadlets for receive. Although particular quadlets 326 * may be in different parts of the 1394 header, the fields within 327 * the quadlets remain in a consistent location. 328 */ 329 typedef struct hci1394_basic_packet { 330 uint32_t q1; /* (HCI format) packet header w/tcode */ 331 uint32_t q2; 332 uint32_t q3; 333 uint32_t q4; 334 uint32_t q5; /* xferstatus/rescount for AR/IR */ 335 } hci1394_basic_pkt_t; 336 337 338 /* defs for the # of bytes are used in building the immediate descriptors */ 339 /* These are used to set REQCOUNT in the HDR etc... */ 340 #define DESC_FIVE_QUADS 20 341 #define DESC_FOUR_QUADS 16 342 #define DESC_THREE_QUADS 12 343 #define DESC_TWO_QUADS 8 344 #define DESC_ONE_QUAD 4 345 #define DESC_ONE_OCTLET 8 346 #define DESC_TWO_OCTLETS 16 347 348 #define DESC_PKT_HDRLEN_AT_READQUAD DESC_THREE_QUADS 349 #define DESC_PKT_HDRLEN_AT_WRITEQUAD DESC_FOUR_QUADS 350 #define DESC_PKT_HDRLEN_AT_READBLOCK DESC_FOUR_QUADS 351 #define DESC_PKT_HDRLEN_AT_WRITEBLOCK DESC_FOUR_QUADS 352 #define DESC_PKT_HDRLEN_AT_LOCK DESC_FOUR_QUADS 353 #define DESC_PKT_HDRLEN_AT_PHY DESC_THREE_QUADS 354 #define DESC_PKT_HDRLEN_AT_WRITE_RESP DESC_THREE_QUADS 355 #define DESC_PKT_HDRLEN_AT_READQUAD_RESP DESC_FOUR_QUADS 356 #define DESC_PKT_HDRLEN_AT_READBLOCK_RESP DESC_FOUR_QUADS 357 #define DESC_PKT_HDRLEN_AT_LOCK_RESP DESC_FOUR_QUADS 358 #define DESC_PKT_HDRLEN_AT_STREAM DESC_TWO_QUADS 359 #define DESC_PKT_HDRLEN_AT_ISOCH DESC_PKT_HDRLEN_AT_STREAM 360 361 /* q1 shortcuts for ASYNC processing */ 362 #define DESC_AT_SRCBUSID 0x00800000 363 #define DESC_ATREQ_Q1_PHY 0x000000E0 364 #define DESC_ATREQ_Q1_QWR 0x00000100 365 #define DESC_ATREQ_Q1_BWR 0x00000110 366 #define DESC_ATREQ_Q1_QRD 0x00000140 367 #define DESC_ATREQ_Q1_BRD 0x00000150 368 #define DESC_ATREQ_Q1_LCK 0x00000190 369 #define DESC_ATRESP_Q1_WR 0x00000120 370 #define DESC_ATRESP_Q1_QRD 0x00000160 371 #define DESC_ATRESP_Q1_BRD 0x00000170 372 #define DESC_ATRESP_Q1_LCK 0x000001B0 373 374 /* q1 - definitions for the asynch packet first quadlet */ 375 #define DESC_PKT_SRCBUSID_SHIFT 23 376 #define DESC_PKT_SRCBUSID_MASK 0x00800000 377 #define DESC_PKT_SPD_SHIFT 16 /* asynch and isoch */ 378 #define DESC_PKT_SPD_MASK 0x00070000 379 #define DESC_PKT_TLABEL_SHIFT 10 /* asynch and isoch */ 380 #define DESC_PKT_TLABEL_MASK 0x0000FC00 381 #define DESC_PKT_RT_SHIFT 8 382 #define DESC_PKT_RT_MASK 0x00000300 383 #define DESC_PKT_TCODE_SHIFT 4 /* asynch and isoch */ 384 #define DESC_PKT_TCODE_MASK 0x000000F0 385 #define DESC_RT_RETRYX 0x1 386 387 /* q1 - definitions for the isoch first quadlet (see q1 async above for spd) */ 388 #define DESC_PKT_TAG_SHIFT 14 389 #define DESC_PKT_TAG_MASK 0x0000C000 390 #define DESC_PKT_CHAN_SHIFT 8 391 #define DESC_PKT_CHAN_MASK 0x00003F00 392 #define DESC_PKT_SY_SHIFT 0 393 #define DESC_PKT_SY_MASK 0x0000000F 394 395 /* q2 - definitions for the asynch second quadlet */ 396 #define DESC_PKT_DESTID_SHIFT 16 /* 1st quadlet for AR */ 397 #define DESC_PKT_DESTID_MASK 0xFFFF0000 398 #define DESC_PKT_SRCID_SHIFT 16 /* asynch recv only */ 399 #define DESC_PKT_SRCID_MASK 0xFFFF0000 400 #define DESC_PKT_DESTOFFHI_SHIFT 0 401 #define DESC_PKT_DESTOFFHI_MASK 0x0000FFFF 402 403 #define DESC_PKT_BUSID_SHIFT 22 /* in srcid or destid */ 404 #define DESC_PKT_BUSID_MASK 0xFFC00000 /* in srcid or destid */ 405 #define DESC_PKT_NODENUM_SHIFT 16 /* in srcid or destid */ 406 #define DESC_PKT_NODENUM_MASK 0x003F0000 /* in srcid or destid */ 407 #define DESC_PKT_RC_SHIFT 12 /* AT/AR read respnse */ 408 #define DESC_PKT_RC_MASK 0x0000F000 /* AT/AR read respnse */ 409 410 /* q3 - definitions for the asynch third quadlet */ 411 #define DESC_PKT_DESTOFFLO_SHIFT 0 412 #define DESC_PKT_DESTOFFLO_MASK 0xFFFFFFFF 413 #define DESC_PKT_PHYGEN_SHIFT 16 414 #define DESC_PKT_PHYGEN_MASK 0x00FF0000 415 416 /* q4 - definitions for the fourth quadlet */ 417 #define DESC_PKT_QDATA_SHIFT 0 /* at_wr_quad, at_rd_resp_quad */ 418 #define DESC_PKT_QDATA_MASK 0xFFFFFFFF 419 #define DESC_PKT_DATALEN_SHIFT 16 /* at_rd_blk, at_wr_blk, isoch (q2), */ 420 #define DESC_PKT_DATALEN_MASK 0xFFFF0000 /* at_rd_resp_blk, at_lock_resp, */ 421 /* ar_rd_blk, ar_wr_blk, ar_lock, */ 422 /* ar_rd_resp, ar_lock_resp */ 423 #define DESC_PKT_EXTTCODE_MASK 0x0000FFFF 424 425 /* 426 * MACROS for getting and setting HCI packet fields 427 */ 428 429 /* ASYNCHRONOUS */ 430 #define HCI1394_DESC_TCODE_GET(data) \ 431 (((data) & DESC_PKT_TCODE_MASK) >> DESC_PKT_TCODE_SHIFT) 432 #define HCI1394_DESC_TLABEL_GET(data) \ 433 (((data) & DESC_PKT_TLABEL_MASK) >> DESC_PKT_TLABEL_SHIFT) 434 #define HCI1394_DESC_RCODE_GET(data) \ 435 (((data) & DESC_PKT_RC_MASK) >> DESC_PKT_RC_SHIFT) 436 #define HCI1394_DESC_DESTID_GET(data) \ 437 (((data) & DESC_PKT_DESTID_MASK) >> DESC_PKT_DESTID_SHIFT) 438 #define HCI1394_DESC_SRCID_GET(data) \ 439 (((data) & DESC_PKT_SRCID_MASK) >> DESC_PKT_SRCID_SHIFT) 440 #define HCI1394_DESC_DATALEN_GET(data) \ 441 (((data) & DESC_PKT_DATALEN_MASK) >> DESC_PKT_DATALEN_SHIFT) 442 #define HCI1394_DESC_EXTTCODE_GET(data) \ 443 ((data) & DESC_PKT_EXTTCODE_MASK) 444 #define HCI1394_DESC_PHYGEN_GET(data) \ 445 (((data) & DESC_PKT_PHYGEN_MASK) >> DESC_PKT_PHYGEN_SHIFT) 446 447 #define HCI1394_DESC_TLABEL_SET(data) \ 448 (((data) << DESC_PKT_TLABEL_SHIFT) & DESC_PKT_TLABEL_MASK) 449 #define HCI1394_DESC_RCODE_SET(data) \ 450 (((data) << DESC_PKT_RC_SHIFT) & DESC_PKT_RC_MASK) 451 #define HCI1394_DESC_DESTID_SET(data) \ 452 (((data) << DESC_PKT_DESTID_SHIFT) & DESC_PKT_DESTID_MASK) 453 #define HCI1394_DESC_DATALEN_SET(data) \ 454 (((data) << DESC_PKT_DATALEN_SHIFT) & DESC_PKT_DATALEN_MASK) 455 #define HCI1394_DESC_EXTTCODE_SET(data) \ 456 ((data) & DESC_PKT_EXTTCODE_MASK) 457 458 459 /* ISOCHRONOUS */ 460 /* 461 * note: the GET macros for isoch take the actual quadlet as an arg because 462 * the location of the IR header quadlet varies depending on the mode. 463 * SETs are expected to be done only for isochronous transmit. 464 */ 465 #define HCI1394_GETTAG(Q) (((Q) & DESC_TAG_MASK) >> DESC_TAG_SHIFT) 466 467 #define HCI1394_SETTAG(PKT, VAL) ((PKT)->q1 = (((PKT)->q1) & \ 468 ~DESC_PKT_TAG_MASK) | (((VAL) << DESC_PKT_TAG_SHIFT) & \ 469 DESC_PKT_TAG_MASK)) 470 471 #define HCI1394_GETCHAN(Q) (((Q) & PKT_CHAN_MASK) >> \ 472 DESC_PKT_CHAN_SHIFT) 473 474 #define HCI1394_SETCHAN(PKT, VAL) ((PKT)->q1 = ((PKT)->q1) & \ 475 ~DESC_PKT_CHAN_MASK) | (((VAL) << DESC_PKT_CHAN_SHIFT) & \ 476 DESC_PKT_CHAN_MASK)) 477 478 #define HCI1394_GETSY(Q) (((Q) & DESC_PKT_SY_MASK) >> \ 479 DESC_PKT_SY_SHIFT) 480 481 #define HCI1394_SETSY(PKT, VAL) ((PKT)->q1 = ((PKT)->q1) & \ 482 ~DESC_PKT_SY_MASK) | (((VAL) << DESC_PKT_SY_SHIFT) & DESC_PKT_SY_MASK)) 483 484 #define HCI1394_GET_ILEN(Q) (((Q) & DESC_DATALEN_MASK) >> \ 485 DESC_DATALEN_SHIFT) 486 487 #define HCI1394_SET_ILEN(PKT, VAL) ((PKT)->q2 = (((PKT)->q1) & \ 488 ~DESC_PKT_DATALEN_MASK) | (((VAL) << DESC_PKT_DATALEN_SHIFT) & \ 489 DESC_PKT_DATALEN_MASK)) 490 491 #define HCI1394_IT_SET_HDR_Q1(PKT, SPD, TAG, CH, TC, SY) ((PKT)->q1 = 0 | \ 492 (((SPD) << DESC_PKT_SPD_SHIFT) & DESC_PKT_SPD_MASK) | \ 493 (((TAG) << DESC_PKT_TAG_SHIFT) & DESC_PKT_TAG_MASK) | \ 494 (((CH) << DESC_PKT_CH_SHIFT) & DESC_PKT_CH_MASK) | \ 495 (((TC) << DESC_PKT_TCODE_SHIFT) & DESC_PKT_TCODE_MASK) | \ 496 (((SY) << DESC_PKT_SY_SHIFT) & DESC_PKT_SY_MASK)) 497 498 /* 499 * OpenHCI Packet format sizes (header only) 500 */ 501 #define DESC_SZ_AR_WRITEQUAD_REQ DESC_FIVE_QUADS 502 #define DESC_SZ_AR_WRITEBLOCK_REQ DESC_FIVE_QUADS /* add data_len */ 503 #define DESC_SZ_AR_WRITE_RESP DESC_FOUR_QUADS 504 #define DESC_SZ_AR_READQUAD_REQ DESC_FOUR_QUADS 505 #define DESC_SZ_AR_READBLOCK_REQ DESC_FIVE_QUADS 506 #define DESC_SZ_AR_READQUAD_RESP DESC_FIVE_QUADS 507 #define DESC_SZ_AR_READ_BLOCK_RESP DESC_FIVE_QUADS /* add data_len */ 508 #define DESC_SZ_AR_PHY DESC_FOUR_QUADS 509 #define DESC_SZ_AR_LOCK_REQ DESC_FIVE_QUADS /* add data_len */ 510 #define DESC_SZ_AR_LOCK_RESP DESC_FIVE_QUADS /* add data_len */ 511 512 #ifdef __cplusplus 513 } 514 #endif 515 516 #endif /* _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H */ 517