| /linux/arch/loongarch/include/asm/ |
| H A D | asmmacro.h | 47 andi \tmp, \tmp, FPU_CSR_TM
48 beqz \tmp, 1f
50 x86mftop \tmp
133 PTR_ADD \tmp, \tmp, \thread
170 PTR_ADD \tmp, \tmp, \thread
207 PTR_ADD \tmp, \thread, \tmp
244 PTR_ADD \tmp, \thread, \tmp
380 not \tmp, zero
417 PTR_ADD \tmp, \thread, \tmp
454 PTR_ADD \tmp, \thread, \tmp
[all …]
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| /linux/drivers/staging/fbtft/ |
| H A D | fb_ssd1331.c | 144 tmp[i] = acc; in set_gamma()
154 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], in set_gamma()
155 tmp[7], tmp[8], tmp[9], tmp[10], tmp[11], tmp[12], tmp[13], in set_gamma()
156 tmp[14], tmp[15], tmp[16], tmp[17], tmp[18], tmp[19], tmp[20], in set_gamma()
157 tmp[21], tmp[22], tmp[23], tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
158 tmp[28], tmp[29], tmp[30], tmp[31], tmp[32], tmp[33], tmp[34], in set_gamma()
159 tmp[35], tmp[36], tmp[37], tmp[38], tmp[39], tmp[40], tmp[41], in set_gamma()
160 tmp[42], tmp[43], tmp[44], tmp[45], tmp[46], tmp[47], tmp[48], in set_gamma()
161 tmp[49], tmp[50], tmp[51], tmp[52], tmp[53], tmp[54], tmp[55], in set_gamma()
162 tmp[56], tmp[57], tmp[58], tmp[59], tmp[60], tmp[61], in set_gamma()
[all …]
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| H A D | fb_ssd1351.c | 142 tmp[0], tmp[1], tmp[2], tmp[3], in set_gamma()
143 tmp[4], tmp[5], tmp[6], tmp[7], in set_gamma()
144 tmp[8], tmp[9], tmp[10], tmp[11], in set_gamma()
145 tmp[12], tmp[13], tmp[14], tmp[15], in set_gamma()
146 tmp[16], tmp[17], tmp[18], tmp[19], in set_gamma()
147 tmp[20], tmp[21], tmp[22], tmp[23], in set_gamma()
148 tmp[24], tmp[25], tmp[26], tmp[27], in set_gamma()
149 tmp[28], tmp[29], tmp[30], tmp[31], in set_gamma()
150 tmp[32], tmp[33], tmp[34], tmp[35], in set_gamma()
151 tmp[36], tmp[37], tmp[38], tmp[39], in set_gamma()
[all …]
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mmhub_v3_0_2.c | 236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, in mmhub_v3_0_2_init_cache_regs()
254 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v3_0_2_init_cache_regs()
258 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v3_0_2_init_cache_regs()
280 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, in mmhub_v3_0_2_enable_system_domain()
322 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_2_setup_vmid_config()
324 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_2_setup_vmid_config()
327 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_2_setup_vmid_config()
329 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_2_setup_vmid_config()
331 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_2_setup_vmid_config()
333 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_2_setup_vmid_config()
[all …]
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| H A D | mmhub_v3_3.c | 233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, in mmhub_v3_3_init_cache_regs()
251 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v3_3_init_cache_regs()
255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v3_3_init_cache_regs()
277 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, in mmhub_v3_3_enable_system_domain()
314 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_3_setup_vmid_config()
316 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_3_setup_vmid_config()
319 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_3_setup_vmid_config()
321 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_3_setup_vmid_config()
323 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_3_setup_vmid_config()
325 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_3_setup_vmid_config()
[all …]
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| H A D | gfxhub_v3_0_3.c | 223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v3_0_3_init_cache_regs()
226 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v3_0_3_init_cache_regs()
241 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v3_0_3_init_cache_regs()
245 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v3_0_3_init_cache_regs()
267 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v3_0_3_enable_system_domain()
306 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
308 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
310 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
312 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
314 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
[all …]
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| H A D | gfxhub_v1_0.c | 198 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_0_init_cache_regs()
202 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_0_init_cache_regs()
228 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in gfxhub_v1_0_enable_system_domain()
269 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
271 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
274 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
276 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
278 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
280 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
359 tmp = REG_SET_FIELD(tmp, in gfxhub_v1_0_gart_disable()
[all …]
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| H A D | gfxhub_v2_0.c | 217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v2_0_init_cache_regs()
220 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v2_0_init_cache_regs()
235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v2_0_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v2_0_init_cache_regs()
261 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v2_0_enable_system_domain()
294 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
296 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
298 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
300 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
302 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
[all …]
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| H A D | gfxhub_v11_5_0.c | 221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v11_5_0_init_cache_regs()
224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v11_5_0_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v11_5_0_init_cache_regs()
243 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v11_5_0_init_cache_regs()
265 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v11_5_0_enable_system_domain()
304 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v11_5_0_setup_vmid_config()
306 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v11_5_0_setup_vmid_config()
308 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v11_5_0_setup_vmid_config()
310 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v11_5_0_setup_vmid_config()
312 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v11_5_0_setup_vmid_config()
[all …]
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| H A D | gfxhub_v3_0.c | 218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v3_0_init_cache_regs()
221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v3_0_init_cache_regs()
236 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v3_0_init_cache_regs()
240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v3_0_init_cache_regs()
262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v3_0_enable_system_domain()
301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
[all …]
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| H A D | gfxhub_v12_0.c | 226 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v12_0_init_cache_regs()
229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v12_0_init_cache_regs()
244 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v12_0_init_cache_regs()
248 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, in gfxhub_v12_0_init_cache_regs()
270 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, in gfxhub_v12_0_enable_system_domain()
309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v12_0_setup_vmid_config()
311 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v12_0_setup_vmid_config()
313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v12_0_setup_vmid_config()
315 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v12_0_setup_vmid_config()
317 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, in gfxhub_v12_0_setup_vmid_config()
[all …]
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| H A D | mmhub_v3_0_1.c | 237 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, in mmhub_v3_0_1_init_cache_regs()
255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v3_0_1_init_cache_regs()
259 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v3_0_1_init_cache_regs()
281 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, in mmhub_v3_0_1_enable_system_domain()
317 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_1_setup_vmid_config()
319 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_1_setup_vmid_config()
322 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_1_setup_vmid_config()
324 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_1_setup_vmid_config()
326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_1_setup_vmid_config()
328 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_1_setup_vmid_config()
[all …]
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| H A D | mmhub_v3_0.c | 244 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, in mmhub_v3_0_init_cache_regs()
262 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v3_0_init_cache_regs()
266 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v3_0_init_cache_regs()
288 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, in mmhub_v3_0_enable_system_domain()
330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_setup_vmid_config()
332 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_setup_vmid_config()
335 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_setup_vmid_config()
337 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_setup_vmid_config()
339 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_setup_vmid_config()
341 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v3_0_setup_vmid_config()
[all …]
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| H A D | mmhub_v4_1_0.c | 245 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, in mmhub_v4_1_0_init_cache_regs()
263 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v4_1_0_init_cache_regs()
267 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v4_1_0_init_cache_regs()
289 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, in mmhub_v4_1_0_enable_system_domain()
331 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v4_1_0_setup_vmid_config()
333 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v4_1_0_setup_vmid_config()
336 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v4_1_0_setup_vmid_config()
338 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v4_1_0_setup_vmid_config()
340 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v4_1_0_setup_vmid_config()
342 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v4_1_0_setup_vmid_config()
[all …]
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| H A D | mmhub_v2_3.c | 212 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, in mmhub_v2_3_init_cache_regs()
230 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v2_3_init_cache_regs()
234 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v2_3_init_cache_regs()
256 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, in mmhub_v2_3_enable_system_domain()
292 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_3_setup_vmid_config()
294 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_3_setup_vmid_config()
297 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_3_setup_vmid_config()
299 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_3_setup_vmid_config()
301 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_3_setup_vmid_config()
303 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_3_setup_vmid_config()
[all …]
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| H A D | mmhub_v2_0.c | 288 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, in mmhub_v2_0_init_cache_regs()
306 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v2_0_init_cache_regs()
310 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, in mmhub_v2_0_init_cache_regs()
332 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, in mmhub_v2_0_enable_system_domain()
374 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_0_setup_vmid_config()
376 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_0_setup_vmid_config()
379 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_0_setup_vmid_config()
381 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_0_setup_vmid_config()
383 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_0_setup_vmid_config()
385 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, in mmhub_v2_0_setup_vmid_config()
[all …]
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| H A D | lsdma_v6_0.c | 45 uint32_t tmp; in lsdma_v6_0_copy_mem() local
56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v6_0_copy_mem()
57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v6_0_copy_mem()
58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v6_0_copy_mem()
59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v6_0_copy_mem()
60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v6_0_copy_mem()
62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v6_0_copy_mem()
78 uint32_t tmp; in lsdma_v6_0_fill_mem() local
89 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v6_0_fill_mem()
90 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v6_0_fill_mem()
[all …]
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| H A D | lsdma_v7_0.c | 45 uint32_t tmp; in lsdma_v7_0_copy_mem() local
56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v7_0_copy_mem()
57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v7_0_copy_mem()
58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v7_0_copy_mem()
59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v7_0_copy_mem()
60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v7_0_copy_mem()
62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v7_0_copy_mem()
78 uint32_t tmp; in lsdma_v7_0_fill_mem() local
89 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v7_0_fill_mem()
90 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v7_0_fill_mem()
[all …]
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| H A D | mmhub_v1_8.c | 230 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, in mmhub_v1_8_init_cache_regs()
233 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, in mmhub_v1_8_init_cache_regs()
237 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, in mmhub_v1_8_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, in mmhub_v1_8_init_cache_regs()
252 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in mmhub_v1_8_init_cache_regs()
256 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in mmhub_v1_8_init_cache_regs()
264 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, in mmhub_v1_8_init_cache_regs()
266 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, in mmhub_v1_8_init_cache_regs()
269 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, in mmhub_v1_8_init_cache_regs()
271 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, in mmhub_v1_8_init_cache_regs()
[all …]
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| H A D | gfxhub_v1_2.c | 247 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_2_xcc_init_cache_regs()
251 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, in gfxhub_v1_2_xcc_init_cache_regs()
282 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in gfxhub_v1_2_xcc_enable_system_domain()
339 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
341 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
344 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
346 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
348 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
350 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gfxhub_v1_2_xcc_setup_vmid_config()
454 tmp = REG_SET_FIELD(tmp, in gfxhub_v1_2_xcc_gart_disable()
[all …]
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_clocks.c | 453 tmp |= 1; in radeon_legacy_set_engine_clock()
456 tmp |= 2; in radeon_legacy_set_engine_clock()
459 tmp |= 3; in radeon_legacy_set_engine_clock()
462 tmp |= 4; in radeon_legacy_set_engine_clock()
486 tmp &= in radeon_legacy_set_clock_gating()
490 tmp &= in radeon_legacy_set_clock_gating()
501 tmp &= in radeon_legacy_set_clock_gating()
516 tmp |= in radeon_legacy_set_clock_gating()
557 tmp &= in radeon_legacy_set_clock_gating()
624 tmp &= in radeon_legacy_set_clock_gating()
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| H A D | vce_v2_0.c | 41 u32 tmp; in vce_v2_0_set_sw_cg() local
45 tmp |= 0xe70000; in vce_v2_0_set_sw_cg()
53 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
59 tmp |= 0xe7; in vce_v2_0_set_sw_cg()
69 tmp |= 0x3fc; in vce_v2_0_set_sw_cg()
76 u32 orig, tmp; in vce_v2_0_set_dyn_cg() local
83 tmp |= 0xe1; in vce_v2_0_set_dyn_cg()
91 if (tmp != orig) in vce_v2_0_set_dyn_cg()
95 tmp &= ~0x3fc; in vce_v2_0_set_dyn_cg()
133 u32 tmp; in vce_v2_0_init_cg() local
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| H A D | rs400.c | 67 uint32_t tmp; in rs400_gart_tlb_flush() local
114 uint32_t tmp; in rs400_gart_enable() local
200 uint32_t tmp; in rs400_gart_disable() local
244 uint32_t tmp; in rs400_mc_wait_for_idle() local
312 uint32_t tmp; in rs400_debugfs_gart_info_show() local
347 tmp = RREG32_MC(0x5F); in rs400_debugfs_gart_info_show()
353 tmp = RREG32_MC(0x3B); in rs400_debugfs_gart_info_show()
355 tmp = RREG32_MC(0x3C); in rs400_debugfs_gart_info_show()
357 tmp = RREG32_MC(0x30); in rs400_debugfs_gart_info_show()
359 tmp = RREG32_MC(0x31); in rs400_debugfs_gart_info_show()
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| /linux/drivers/scsi/mvsas/ |
| H A D | mv_64xx.c | 31 u32 tmp; in mvs_64xx_enable_xmt() local
81 tmp = reg; in mvs_64xx_stp_reset()
106 u32 tmp; in mvs_64xx_phy_reset() local
127 u32 tmp; in mvs_64xx_clear_srs_irq() local
147 u32 tmp; in mvs_64xx_chip_reset() local
197 u32 tmp; in mvs_64xx_phy_disable() local
219 u32 tmp; in mvs_64xx_phy_enable() local
378 tmp = 0; in mvs_64xx_init()
423 u32 tmp; in mvs_64xx_interrupt_enable() local
432 u32 tmp; in mvs_64xx_interrupt_disable() local
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| /linux/drivers/video/fbdev/kyro/ |
| H A D | STG4000Ramdac.c | 29 u32 tmp = 0; in InitialiseRamdac() local
37 if (tmp & 0x1) { in InitialiseRamdac()
53 tmp |= _16BPP; in InitialiseRamdac()
60 tmp |= _32BPP; in InitialiseRamdac()
76 tmp = STG_READ_REG(DACPrimSize); in InitialiseRamdac()
79 tmp |= in InitialiseRamdac()
90 tmp = STG_READ_REG(DACPLLMode); in InitialiseRamdac()
94 STG_WRITE_REG(DACPLLMode, tmp); in InitialiseRamdac()
104 tmp &= ~SET_BIT(31); in InitialiseRamdac()
149 u32 tmp; in DisableRamdacOutput() local
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