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Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 47) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_irq.c699 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()
730 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()
787 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_outbox_irq_state()
813 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_trace_irq_state()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_ai.c246 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()
304 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
H A Dmxgpu_nv.c279 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_ack_irq()
343 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_rcv_irq()
H A Damdgpu_irq.h43 AMDGPU_IRQ_STATE_ENABLE, enumerator
H A Dmxgpu_vi.c507 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()
540 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
H A Dnbio_v7_4.c466 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()
511 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
H A Dsi_dma.c595 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
611 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
H A Dvce_v2_0.c552 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
H A Damdgpu_irq.c538 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
H A Dvpe_v6_1.c323 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in vpe_v6_1_set_trap_irq_state()
H A Dsdma_v2_4.c1003 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
1019 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
H A Dgfx_v12_0.c4666 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_gfx_eop_interrupt_state()
4717 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_compute_eop_interrupt_state()
4825 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_priv_reg_fault_state()
4834 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_reg_fault_state()
4848 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_reg_fault_state()
4871 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_bad_op_fault_state()
4880 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_bad_op_fault_state()
4894 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_bad_op_fault_state()
4916 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v12_0_set_priv_inst_fault_state()
4925 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v12_0_set_priv_inst_fault_state()
H A Dgfx_v9_4_3.c3113 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3160 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_reg_fault_state()
3164 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_reg_fault_state()
3174 state == AMDGPU_IRQ_STATE_ENABLE ? in gfx_v9_4_3_set_priv_reg_fault_state()
3200 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_bad_op_fault_state()
3204 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_bad_op_fault_state()
3214 state == AMDGPU_IRQ_STATE_ENABLE ? in gfx_v9_4_3_set_bad_op_fault_state()
3239 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_inst_fault_state()
3243 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_inst_fault_state()
H A Dcik_sdma.c1112 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1128 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
H A Dgfx_v9_0.c5946 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()
5949 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()
5998 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()
6044 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()
6047 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
6057 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
6080 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_bad_op_fault_state()
6083 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_bad_op_fault_state()
6113 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()
6116 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()
[all …]
H A Dnbio_v4_3.c574 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); in nbio_v4_3_set_ras_err_event_athub_irq_state()
H A Dsdma_v3_0.c1339 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
1355 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
H A Dgfx_v11_0.c6132 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_gfx_eop_interrupt_state()
6189 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_compute_eop_interrupt_state()
6297 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_reg_fault_state()
6306 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6320 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6343 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_bad_op_fault_state()
6352 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6366 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6388 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_inst_fault_state()
6397 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
H A Dgmc_v6_0.c1041 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
H A Dgmc_v11_0.c80 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v11_0_vm_fault_interrupt_state()
H A Dgmc_v12_0.c70 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v12_0_vm_fault_interrupt_state()
H A Dgfx_v6_0.c3209 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()
3238 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()
3272 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()
3297 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
H A Dvce_v3_0.c734 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
H A Dgmc_v10_0.c80 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
H A Dgmc_v9_0.c444 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_ecc_interrupt_state()
510 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()

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