1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RoCE HSI File - Autogenerated 37 */ 38 39 #ifndef __BNXT_RE_HSI_H__ 40 #define __BNXT_RE_HSI_H__ 41 42 /* include bnxt_hsi.h from bnxt_en driver */ 43 #include "bnxt_hsi.h" 44 45 /* tx_doorbell (size:32b/4B) */ 46 struct tx_doorbell { 47 __le32 key_idx; 48 #define TX_DOORBELL_IDX_MASK 0xffffffUL 49 #define TX_DOORBELL_IDX_SFT 0 50 #define TX_DOORBELL_KEY_MASK 0xf0000000UL 51 #define TX_DOORBELL_KEY_SFT 28 52 #define TX_DOORBELL_KEY_TX (0x0UL << 28) 53 #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX 54 }; 55 56 /* rx_doorbell (size:32b/4B) */ 57 struct rx_doorbell { 58 __le32 key_idx; 59 #define RX_DOORBELL_IDX_MASK 0xffffffUL 60 #define RX_DOORBELL_IDX_SFT 0 61 #define RX_DOORBELL_KEY_MASK 0xf0000000UL 62 #define RX_DOORBELL_KEY_SFT 28 63 #define RX_DOORBELL_KEY_RX (0x1UL << 28) 64 #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX 65 }; 66 67 /* cmpl_doorbell (size:32b/4B) */ 68 struct cmpl_doorbell { 69 __le32 key_mask_valid_idx; 70 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL 71 #define CMPL_DOORBELL_IDX_SFT 0 72 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL 73 #define CMPL_DOORBELL_MASK 0x8000000UL 74 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL 75 #define CMPL_DOORBELL_KEY_SFT 28 76 #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) 77 #define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL 78 }; 79 80 /* status_doorbell (size:32b/4B) */ 81 struct status_doorbell { 82 __le32 key_idx; 83 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL 84 #define STATUS_DOORBELL_IDX_SFT 0 85 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL 86 #define STATUS_DOORBELL_KEY_SFT 28 87 #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28) 88 #define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT 89 }; 90 91 /* cmdq_init (size:128b/16B) */ 92 struct cmdq_init { 93 __le64 cmdq_pbl; 94 __le16 cmdq_size_cmdq_lvl; 95 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL 96 #define CMDQ_INIT_CMDQ_LVL_SFT 0 97 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL 98 #define CMDQ_INIT_CMDQ_SIZE_SFT 2 99 __le16 creq_ring_id; 100 __le32 prod_idx; 101 }; 102 103 /* cmdq_base (size:128b/16B) */ 104 struct cmdq_base { 105 u8 opcode; 106 #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL 107 #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL 108 #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL 109 #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL 110 #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL 111 #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL 112 #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL 113 #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL 114 #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL 115 #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL 116 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL 117 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL 118 #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL 119 #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL 120 #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL 121 #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL 122 #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL 123 #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL 124 #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL 125 #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL 126 #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL 127 #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL 128 #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL 129 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL 130 #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL 131 #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL 132 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL 133 #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL 134 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL 135 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL 136 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL 137 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL 138 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL 139 #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL 140 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL 141 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL 142 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL 143 #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 144 #define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL 145 #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL 146 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 147 #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 148 u8 cmd_size; 149 __le16 flags; 150 __le16 cookie; 151 u8 resp_size; 152 u8 reserved8; 153 __le64 resp_addr; 154 }; 155 156 /* creq_base (size:128b/16B) */ 157 struct creq_base { 158 u8 type; 159 #define CREQ_BASE_TYPE_MASK 0x3fUL 160 #define CREQ_BASE_TYPE_SFT 0 161 #define CREQ_BASE_TYPE_QP_EVENT 0x38UL 162 #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL 163 #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT 164 u8 reserved56[7]; 165 u8 v; 166 #define CREQ_BASE_V 0x1UL 167 u8 event; 168 u8 reserved48[6]; 169 }; 170 171 /* cmdq_query_version (size:128b/16B) */ 172 struct cmdq_query_version { 173 u8 opcode; 174 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL 175 #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 176 u8 cmd_size; 177 __le16 flags; 178 __le16 cookie; 179 u8 resp_size; 180 u8 reserved8; 181 __le64 resp_addr; 182 }; 183 184 /* creq_query_version_resp (size:128b/16B) */ 185 struct creq_query_version_resp { 186 u8 type; 187 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL 188 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 189 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL 190 #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 191 u8 status; 192 __le16 cookie; 193 u8 fw_maj; 194 u8 fw_minor; 195 u8 fw_bld; 196 u8 fw_rsvd; 197 u8 v; 198 #define CREQ_QUERY_VERSION_RESP_V 0x1UL 199 u8 event; 200 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL 201 #define CREQ_QUERY_VERSION_RESP_EVENT_LAST \ 202 CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 203 __le16 reserved16; 204 u8 intf_maj; 205 u8 intf_minor; 206 u8 intf_bld; 207 u8 intf_rsvd; 208 }; 209 210 /* cmdq_initialize_fw (size:896b/112B) */ 211 struct cmdq_initialize_fw { 212 u8 opcode; 213 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL 214 #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 215 u8 cmd_size; 216 __le16 flags; 217 #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 218 #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL 219 __le16 cookie; 220 u8 resp_size; 221 u8 reserved8; 222 __le64 resp_addr; 223 u8 qpc_pg_size_qpc_lvl; 224 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL 225 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 226 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL 227 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL 228 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL 229 #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 230 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL 231 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 232 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4) 233 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4) 234 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4) 235 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4) 236 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4) 237 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4) 238 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G 239 u8 mrw_pg_size_mrw_lvl; 240 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL 241 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 242 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL 243 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL 244 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL 245 #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 246 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL 247 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 248 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4) 249 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4) 250 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4) 251 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4) 252 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4) 253 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4) 254 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G 255 u8 srq_pg_size_srq_lvl; 256 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL 257 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 258 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL 259 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL 260 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL 261 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 262 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL 263 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 264 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 265 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 266 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 267 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 268 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 269 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 270 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G 271 u8 cq_pg_size_cq_lvl; 272 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL 273 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 274 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL 275 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL 276 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL 277 #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 278 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL 279 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 280 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4) 281 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4) 282 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4) 283 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4) 284 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4) 285 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4) 286 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G 287 u8 tqm_pg_size_tqm_lvl; 288 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL 289 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 290 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL 291 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL 292 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL 293 #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 294 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL 295 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 296 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4) 297 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4) 298 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4) 299 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4) 300 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4) 301 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4) 302 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G 303 u8 tim_pg_size_tim_lvl; 304 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL 305 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 306 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL 307 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL 308 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL 309 #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 310 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL 311 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 312 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4) 313 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4) 314 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4) 315 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4) 316 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4) 317 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4) 318 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G 319 __le16 log2_dbr_pg_size; 320 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL 321 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 322 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL 323 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL 324 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL 325 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL 326 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL 327 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL 328 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL 329 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL 330 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL 331 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL 332 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL 333 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL 334 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL 335 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL 336 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL 337 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL 338 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \ 339 CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 340 #define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL 341 #define CMDQ_INITIALIZE_FW_RSVD_SFT 4 342 __le64 qpc_page_dir; 343 __le64 mrw_page_dir; 344 __le64 srq_page_dir; 345 __le64 cq_page_dir; 346 __le64 tqm_page_dir; 347 __le64 tim_page_dir; 348 __le32 number_of_qp; 349 __le32 number_of_mrw; 350 __le32 number_of_srq; 351 __le32 number_of_cq; 352 __le32 max_qp_per_vf; 353 __le32 max_mrw_per_vf; 354 __le32 max_srq_per_vf; 355 __le32 max_cq_per_vf; 356 __le32 max_gid_per_vf; 357 __le32 stat_ctx_id; 358 }; 359 360 /* creq_initialize_fw_resp (size:128b/16B) */ 361 struct creq_initialize_fw_resp { 362 u8 type; 363 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 364 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 365 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 366 #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 367 u8 status; 368 __le16 cookie; 369 __le32 reserved32; 370 u8 v; 371 #define CREQ_INITIALIZE_FW_RESP_V 0x1UL 372 u8 event; 373 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL 374 #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST \ 375 CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 376 u8 reserved48[6]; 377 }; 378 379 /* cmdq_deinitialize_fw (size:128b/16B) */ 380 struct cmdq_deinitialize_fw { 381 u8 opcode; 382 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL 383 #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST \ 384 CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 385 u8 cmd_size; 386 __le16 flags; 387 __le16 cookie; 388 u8 resp_size; 389 u8 reserved8; 390 __le64 resp_addr; 391 }; 392 393 /* creq_deinitialize_fw_resp (size:128b/16B) */ 394 struct creq_deinitialize_fw_resp { 395 u8 type; 396 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 397 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 398 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 399 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 400 u8 status; 401 __le16 cookie; 402 __le32 reserved32; 403 u8 v; 404 #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL 405 u8 event; 406 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL 407 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST \ 408 CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 409 u8 reserved48[6]; 410 }; 411 412 /* cmdq_create_qp (size:832b/104B) */ 413 struct cmdq_create_qp { 414 u8 opcode; 415 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL 416 #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP 417 u8 cmd_size; 418 __le16 flags; 419 __le16 cookie; 420 u8 resp_size; 421 u8 reserved8; 422 __le64 resp_addr; 423 __le64 qp_handle; 424 __le32 qp_flags; 425 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL 426 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL 427 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 428 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL 429 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL 430 #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL 431 #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL 432 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL 433 #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED 0x100UL 434 #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID 0x200UL 435 #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED 0x400UL 436 #define CMDQ_CREATE_QP_QP_FLAGS_LAST \ 437 CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED 438 u8 type; 439 #define CMDQ_CREATE_QP_TYPE_RC 0x2UL 440 #define CMDQ_CREATE_QP_TYPE_UD 0x4UL 441 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL 442 #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL 443 #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI 444 u8 sq_pg_size_sq_lvl; 445 #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL 446 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 447 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL 448 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL 449 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL 450 #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2 451 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL 452 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 453 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4) 454 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4) 455 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4) 456 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4) 457 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4) 458 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4) 459 #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G 460 u8 rq_pg_size_rq_lvl; 461 #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL 462 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 463 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL 464 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL 465 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL 466 #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2 467 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL 468 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 469 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4) 470 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4) 471 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4) 472 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4) 473 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4) 474 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4) 475 #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G 476 u8 unused_0; 477 __le32 dpi; 478 __le32 sq_size; 479 __le32 rq_size; 480 __le16 sq_fwo_sq_sge; 481 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL 482 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 483 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL 484 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 485 __le16 rq_fwo_rq_sge; 486 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL 487 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 488 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL 489 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 490 __le32 scq_cid; 491 __le32 rcq_cid; 492 __le32 srq_cid; 493 __le32 pd_id; 494 __le64 sq_pbl; 495 __le64 rq_pbl; 496 __le64 irrq_addr; 497 __le64 orrq_addr; 498 __le32 request_xid; 499 __le16 steering_tag; 500 __le16 reserved16; 501 }; 502 503 /* creq_create_qp_resp (size:128b/16B) */ 504 struct creq_create_qp_resp { 505 u8 type; 506 #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL 507 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 508 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL 509 #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 510 u8 status; 511 __le16 cookie; 512 __le32 xid; 513 u8 v; 514 #define CREQ_CREATE_QP_RESP_V 0x1UL 515 u8 event; 516 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL 517 #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 518 u8 optimized_transmit_enabled; 519 u8 reserved48[5]; 520 }; 521 522 /* cmdq_destroy_qp (size:192b/24B) */ 523 struct cmdq_destroy_qp { 524 u8 opcode; 525 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL 526 #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 527 u8 cmd_size; 528 __le16 flags; 529 __le16 cookie; 530 u8 resp_size; 531 u8 reserved8; 532 __le64 resp_addr; 533 __le32 qp_cid; 534 __le32 unused_0; 535 }; 536 537 /* creq_destroy_qp_resp (size:128b/16B) */ 538 struct creq_destroy_qp_resp { 539 u8 type; 540 #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL 541 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 542 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL 543 #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 544 u8 status; 545 __le16 cookie; 546 __le32 xid; 547 u8 v; 548 #define CREQ_DESTROY_QP_RESP_V 0x1UL 549 u8 event; 550 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL 551 #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 552 u8 reserved48[6]; 553 }; 554 555 /* cmdq_modify_qp (size:1024b/128B) */ 556 struct cmdq_modify_qp { 557 u8 opcode; 558 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL 559 #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 560 u8 cmd_size; 561 __le16 flags; 562 __le16 cookie; 563 u8 resp_size; 564 u8 qp_type; 565 #define CMDQ_MODIFY_QP_QP_TYPE_RC 0x2UL 566 #define CMDQ_MODIFY_QP_QP_TYPE_UD 0x4UL 567 #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL 568 #define CMDQ_MODIFY_QP_QP_TYPE_GSI 0x7UL 569 #define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI 570 __le64 resp_addr; 571 __le32 modify_mask; 572 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL 573 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL 574 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL 575 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL 576 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL 577 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL 578 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL 579 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL 580 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL 581 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL 582 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL 583 #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL 584 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL 585 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL 586 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL 587 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL 588 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL 589 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL 590 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL 591 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL 592 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL 593 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL 594 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL 595 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL 596 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL 597 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL 598 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL 599 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL 600 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL 601 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL 602 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL 603 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL 604 __le32 qp_cid; 605 u8 network_type_en_sqd_async_notify_new_state; 606 #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL 607 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 608 #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL 609 #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL 610 #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL 611 #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL 612 #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL 613 #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL 614 #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL 615 #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR 616 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL 617 #define CMDQ_MODIFY_QP_UNUSED1 0x20UL 618 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL 619 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 620 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6) 621 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6) 622 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6) 623 #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 624 u8 access; 625 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL 626 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 627 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL 628 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL 629 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL 630 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL 631 __le16 pkey; 632 __le32 qkey; 633 __le32 dgid[4]; 634 __le32 flow_label; 635 __le16 sgid_index; 636 u8 hop_limit; 637 u8 traffic_class; 638 __le16 dest_mac[3]; 639 u8 tos_dscp_tos_ecn; 640 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL 641 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 642 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL 643 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 644 u8 path_mtu_pingpong_push_enable; 645 #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL 646 #define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL 647 #define CMDQ_MODIFY_QP_UNUSED3_SFT 1 648 #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL 649 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 650 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4) 651 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4) 652 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4) 653 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4) 654 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4) 655 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4) 656 #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 657 u8 timeout; 658 u8 retry_cnt; 659 u8 rnr_retry; 660 u8 min_rnr_timer; 661 __le32 rq_psn; 662 __le32 sq_psn; 663 u8 max_rd_atomic; 664 u8 max_dest_rd_atomic; 665 __le16 enable_cc; 666 #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL 667 #define CMDQ_MODIFY_QP_UNUSED15_MASK 0xfffeUL 668 #define CMDQ_MODIFY_QP_UNUSED15_SFT 1 669 __le32 sq_size; 670 __le32 rq_size; 671 __le16 sq_sge; 672 __le16 rq_sge; 673 __le32 max_inline_data; 674 __le32 dest_qp_id; 675 __le32 pingpong_push_dpi; 676 __le16 src_mac[3]; 677 __le16 vlan_pcp_vlan_dei_vlan_id; 678 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL 679 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 680 #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL 681 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL 682 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 683 __le64 irrq_addr; 684 __le64 orrq_addr; 685 __le32 ext_modify_mask; 686 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL 687 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL 688 __le32 ext_stats_ctx_id; 689 __le16 schq_id; 690 __le16 unused_0; 691 __le32 reserved32; 692 }; 693 694 /* creq_modify_qp_resp (size:128b/16B) */ 695 struct creq_modify_qp_resp { 696 u8 type; 697 #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL 698 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 699 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL 700 #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 701 u8 status; 702 __le16 cookie; 703 __le32 xid; 704 u8 v; 705 #define CREQ_MODIFY_QP_RESP_V 0x1UL 706 u8 event; 707 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL 708 #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 709 u8 pingpong_push_state_index_enabled; 710 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL 711 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL 712 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1 713 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL 714 u8 reserved8; 715 __le32 lag_src_mac; 716 }; 717 718 /* cmdq_query_qp (size:192b/24B) */ 719 struct cmdq_query_qp { 720 u8 opcode; 721 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL 722 #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP 723 u8 cmd_size; 724 __le16 flags; 725 __le16 cookie; 726 u8 resp_size; 727 u8 reserved8; 728 __le64 resp_addr; 729 __le32 qp_cid; 730 __le32 unused_0; 731 }; 732 733 /* creq_query_qp_resp (size:128b/16B) */ 734 struct creq_query_qp_resp { 735 u8 type; 736 #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL 737 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 738 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL 739 #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 740 u8 status; 741 __le16 cookie; 742 __le32 size; 743 u8 v; 744 #define CREQ_QUERY_QP_RESP_V 0x1UL 745 u8 event; 746 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL 747 #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 748 u8 reserved48[6]; 749 }; 750 751 /* creq_query_qp_resp_sb (size:832b/104B) */ 752 struct creq_query_qp_resp_sb { 753 u8 opcode; 754 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL 755 #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 756 u8 status; 757 __le16 cookie; 758 __le16 flags; 759 u8 resp_size; 760 u8 reserved8; 761 __le32 xid; 762 u8 en_sqd_async_notify_state; 763 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL 764 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 765 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL 766 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL 767 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL 768 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL 769 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL 770 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL 771 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL 772 #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR 773 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL 774 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL 775 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5 776 u8 access; 777 #define \ 778 CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK\ 779 0xffUL 780 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT\ 781 0 782 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL 783 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL 784 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL 785 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL 786 __le16 pkey; 787 __le32 qkey; 788 __le32 reserved32; 789 __le32 dgid[4]; 790 __le32 flow_label; 791 __le16 sgid_index; 792 u8 hop_limit; 793 u8 traffic_class; 794 __le16 dest_mac[3]; 795 __le16 path_mtu_dest_vlan_id; 796 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL 797 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 798 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL 799 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 800 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12) 801 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12) 802 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12) 803 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12) 804 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12) 805 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12) 806 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 807 u8 timeout; 808 u8 retry_cnt; 809 u8 rnr_retry; 810 u8 min_rnr_timer; 811 __le32 rq_psn; 812 __le32 sq_psn; 813 u8 max_rd_atomic; 814 u8 max_dest_rd_atomic; 815 u8 tos_dscp_tos_ecn; 816 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL 817 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 818 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL 819 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 820 u8 enable_cc; 821 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL 822 __le32 sq_size; 823 __le32 rq_size; 824 __le16 sq_sge; 825 __le16 rq_sge; 826 __le32 max_inline_data; 827 __le32 dest_qp_id; 828 __le16 port_id; 829 u8 unused_0; 830 u8 stat_collection_id; 831 __le16 src_mac[3]; 832 __le16 vlan_pcp_vlan_dei_vlan_id; 833 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL 834 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 835 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL 836 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL 837 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 838 }; 839 840 /* cmdq_query_qp_extend (size:192b/24B) */ 841 struct cmdq_query_qp_extend { 842 u8 opcode; 843 #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL 844 #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 845 u8 cmd_size; 846 __le16 flags; 847 __le16 cookie; 848 u8 resp_size; 849 u8 num_qps; 850 __le64 resp_addr; 851 __le32 function_id; 852 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL 853 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0 854 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL 855 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8 856 #define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL 857 __le32 current_index; 858 }; 859 860 /* creq_query_qp_extend_resp (size:128b/16B) */ 861 struct creq_query_qp_extend_resp { 862 u8 type; 863 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL 864 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0 865 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL 866 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 867 u8 status; 868 __le16 cookie; 869 __le32 size; 870 u8 v; 871 #define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL 872 u8 event; 873 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL 874 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 875 __le16 reserved16; 876 __le32 current_index; 877 }; 878 879 /* creq_query_qp_extend_resp_sb (size:384b/48B) */ 880 struct creq_query_qp_extend_resp_sb { 881 u8 opcode; 882 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL 883 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST \ 884 CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 885 u8 status; 886 __le16 cookie; 887 __le16 flags; 888 u8 resp_size; 889 u8 reserved8; 890 __le32 xid; 891 u8 state; 892 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL 893 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0 894 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL 895 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL 896 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL 897 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL 898 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL 899 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL 900 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL 901 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 902 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL 903 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4 904 u8 reserved_8; 905 __le16 port_id; 906 __le32 qkey; 907 __le16 sgid_index; 908 u8 network_type; 909 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL 910 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 911 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 912 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST \ 913 CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 914 u8 unused_0; 915 __le32 dgid[4]; 916 __le32 dest_qp_id; 917 u8 stat_collection_id; 918 u8 reservred_8; 919 __le16 reserved_16; 920 }; 921 922 /* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */ 923 struct creq_query_qp_extend_resp_sb_tlv { 924 __le16 cmd_discr; 925 u8 reserved_8b; 926 u8 tlv_flags; 927 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 928 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 929 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 930 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 931 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 932 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 933 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 934 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 935 __le16 tlv_type; 936 __le16 length; 937 u8 total_size; 938 u8 reserved56[7]; 939 u8 opcode; 940 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL 941 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST \ 942 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 943 u8 status; 944 __le16 cookie; 945 __le16 flags; 946 u8 resp_size; 947 u8 reserved8; 948 __le32 xid; 949 u8 state; 950 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL 951 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0 952 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL 953 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL 954 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL 955 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL 956 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL 957 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL 958 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL 959 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST \ 960 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 961 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL 962 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4 963 u8 reserved_8; 964 __le16 port_id; 965 __le32 qkey; 966 __le16 sgid_index; 967 u8 network_type; 968 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL 969 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 970 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 971 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST \ 972 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 973 u8 unused_0; 974 __le32 dgid[4]; 975 __le32 dest_qp_id; 976 u8 stat_collection_id; 977 u8 reservred_8; 978 __le16 reserved_16; 979 }; 980 981 /* cmdq_create_srq (size:448b/56B) */ 982 struct cmdq_create_srq { 983 u8 opcode; 984 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL 985 #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 986 u8 cmd_size; 987 __le16 flags; 988 #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID 0x1UL 989 __le16 cookie; 990 u8 resp_size; 991 u8 reserved8; 992 __le64 resp_addr; 993 __le64 srq_handle; 994 __le16 pg_size_lvl; 995 #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL 996 #define CMDQ_CREATE_SRQ_LVL_SFT 0 997 #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL 998 #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL 999 #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL 1000 #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2 1001 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL 1002 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 1003 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2) 1004 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2) 1005 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2) 1006 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2) 1007 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2) 1008 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2) 1009 #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G 1010 #define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL 1011 #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5 1012 __le16 eventq_id; 1013 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL 1014 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 1015 #define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL 1016 #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12 1017 __le16 srq_size; 1018 __le16 srq_fwo; 1019 __le32 dpi; 1020 __le32 pd_id; 1021 __le64 pbl; 1022 __le16 steering_tag; 1023 u8 reserved48[6]; 1024 }; 1025 1026 /* creq_create_srq_resp (size:128b/16B) */ 1027 struct creq_create_srq_resp { 1028 u8 type; 1029 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL 1030 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 1031 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1032 #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 1033 u8 status; 1034 __le16 cookie; 1035 __le32 xid; 1036 u8 v; 1037 #define CREQ_CREATE_SRQ_RESP_V 0x1UL 1038 u8 event; 1039 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL 1040 #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 1041 u8 reserved48[6]; 1042 }; 1043 1044 /* cmdq_destroy_srq (size:192b/24B) */ 1045 struct cmdq_destroy_srq { 1046 u8 opcode; 1047 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL 1048 #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 1049 u8 cmd_size; 1050 __le16 flags; 1051 __le16 cookie; 1052 u8 resp_size; 1053 u8 reserved8; 1054 __le64 resp_addr; 1055 __le32 srq_cid; 1056 __le32 unused_0; 1057 }; 1058 1059 /* creq_destroy_srq_resp (size:128b/16B) */ 1060 struct creq_destroy_srq_resp { 1061 u8 type; 1062 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL 1063 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 1064 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1065 #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 1066 u8 status; 1067 __le16 cookie; 1068 __le32 xid; 1069 u8 v; 1070 #define CREQ_DESTROY_SRQ_RESP_V 0x1UL 1071 u8 event; 1072 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL 1073 #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 1074 __le16 enable_for_arm[3]; 1075 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL 1076 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0 1077 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL 1078 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 1079 }; 1080 1081 /* cmdq_query_srq (size:192b/24B) */ 1082 struct cmdq_query_srq { 1083 u8 opcode; 1084 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL 1085 #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 1086 u8 cmd_size; 1087 __le16 flags; 1088 __le16 cookie; 1089 u8 resp_size; 1090 u8 reserved8; 1091 __le64 resp_addr; 1092 __le32 srq_cid; 1093 __le32 unused_0; 1094 }; 1095 1096 /* creq_query_srq_resp (size:128b/16B) */ 1097 struct creq_query_srq_resp { 1098 u8 type; 1099 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL 1100 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 1101 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1102 #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 1103 u8 status; 1104 __le16 cookie; 1105 __le32 size; 1106 u8 v; 1107 #define CREQ_QUERY_SRQ_RESP_V 0x1UL 1108 u8 event; 1109 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL 1110 #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 1111 u8 reserved48[6]; 1112 }; 1113 1114 /* creq_query_srq_resp_sb (size:256b/32B) */ 1115 struct creq_query_srq_resp_sb { 1116 u8 opcode; 1117 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL 1118 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 1119 u8 status; 1120 __le16 cookie; 1121 __le16 flags; 1122 u8 resp_size; 1123 u8 reserved8; 1124 __le32 xid; 1125 __le16 srq_limit; 1126 __le16 reserved16; 1127 __le32 data[4]; 1128 }; 1129 1130 /* cmdq_create_cq (size:448b/56B) */ 1131 struct cmdq_create_cq { 1132 u8 opcode; 1133 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL 1134 #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 1135 u8 cmd_size; 1136 __le16 flags; 1137 #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL 1138 #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID 0x2UL 1139 #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE 0x4UL 1140 __le16 cookie; 1141 u8 resp_size; 1142 u8 reserved8; 1143 __le64 resp_addr; 1144 __le64 cq_handle; 1145 __le32 pg_size_lvl; 1146 #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL 1147 #define CMDQ_CREATE_CQ_LVL_SFT 0 1148 #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL 1149 #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL 1150 #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL 1151 #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2 1152 #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL 1153 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 1154 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1155 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1156 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1157 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1158 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1159 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1160 #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G 1161 #define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL 1162 #define CMDQ_CREATE_CQ_UNUSED27_SFT 5 1163 __le32 cq_fco_cnq_id; 1164 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL 1165 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 1166 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL 1167 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 1168 __le32 dpi; 1169 __le32 cq_size; 1170 __le64 pbl; 1171 __le16 steering_tag; 1172 u8 reserved48[6]; 1173 }; 1174 1175 /* creq_create_cq_resp (size:128b/16B) */ 1176 struct creq_create_cq_resp { 1177 u8 type; 1178 #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL 1179 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 1180 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1181 #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 1182 u8 status; 1183 __le16 cookie; 1184 __le32 xid; 1185 u8 v; 1186 #define CREQ_CREATE_CQ_RESP_V 0x1UL 1187 u8 event; 1188 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL 1189 #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 1190 u8 reserved48[6]; 1191 }; 1192 1193 /* cmdq_destroy_cq (size:192b/24B) */ 1194 struct cmdq_destroy_cq { 1195 u8 opcode; 1196 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL 1197 #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 1198 u8 cmd_size; 1199 __le16 flags; 1200 __le16 cookie; 1201 u8 resp_size; 1202 u8 reserved8; 1203 __le64 resp_addr; 1204 __le32 cq_cid; 1205 __le32 unused_0; 1206 }; 1207 1208 /* creq_destroy_cq_resp (size:128b/16B) */ 1209 struct creq_destroy_cq_resp { 1210 u8 type; 1211 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL 1212 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 1213 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL 1214 #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 1215 u8 status; 1216 __le16 cookie; 1217 __le32 xid; 1218 u8 v; 1219 #define CREQ_DESTROY_CQ_RESP_V 0x1UL 1220 u8 event; 1221 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL 1222 #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 1223 __le16 cq_arm_lvl; 1224 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL 1225 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 1226 __le16 total_cnq_events; 1227 __le16 reserved16; 1228 }; 1229 1230 /* cmdq_resize_cq (size:320b/40B) */ 1231 struct cmdq_resize_cq { 1232 u8 opcode; 1233 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL 1234 #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 1235 u8 cmd_size; 1236 __le16 flags; 1237 __le16 cookie; 1238 u8 resp_size; 1239 u8 reserved8; 1240 __le64 resp_addr; 1241 __le32 cq_cid; 1242 __le32 new_cq_size_pg_size_lvl; 1243 #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL 1244 #define CMDQ_RESIZE_CQ_LVL_SFT 0 1245 #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL 1246 #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL 1247 #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL 1248 #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2 1249 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL 1250 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 1251 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1252 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1253 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1254 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1255 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1256 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1257 #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G 1258 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL 1259 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 1260 __le64 new_pbl; 1261 __le32 new_cq_fco; 1262 __le32 unused_0; 1263 }; 1264 1265 /* creq_resize_cq_resp (size:128b/16B) */ 1266 struct creq_resize_cq_resp { 1267 u8 type; 1268 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL 1269 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 1270 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1271 #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 1272 u8 status; 1273 __le16 cookie; 1274 __le32 xid; 1275 u8 v; 1276 #define CREQ_RESIZE_CQ_RESP_V 0x1UL 1277 u8 event; 1278 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL 1279 #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 1280 u8 reserved48[6]; 1281 }; 1282 1283 /* cmdq_allocate_mrw (size:256b/32B) */ 1284 struct cmdq_allocate_mrw { 1285 u8 opcode; 1286 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL 1287 #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 1288 u8 cmd_size; 1289 __le16 flags; 1290 __le16 cookie; 1291 u8 resp_size; 1292 u8 reserved8; 1293 __le64 resp_addr; 1294 __le64 mrw_handle; 1295 u8 mrw_flags; 1296 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL 1297 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 1298 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL 1299 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL 1300 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL 1301 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL 1302 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL 1303 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 1304 #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID 0x10UL 1305 #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK 0xe0UL 1306 #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 5 1307 u8 access; 1308 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL 1309 __le16 steering_tag; 1310 __le32 pd_id; 1311 }; 1312 1313 /* creq_allocate_mrw_resp (size:128b/16B) */ 1314 struct creq_allocate_mrw_resp { 1315 u8 type; 1316 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL 1317 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 1318 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL 1319 #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 1320 u8 status; 1321 __le16 cookie; 1322 __le32 xid; 1323 u8 v; 1324 #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL 1325 u8 event; 1326 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL 1327 #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 1328 u8 reserved48[6]; 1329 }; 1330 1331 /* cmdq_deallocate_key (size:192b/24B) */ 1332 struct cmdq_deallocate_key { 1333 u8 opcode; 1334 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL 1335 #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 1336 u8 cmd_size; 1337 __le16 flags; 1338 __le16 cookie; 1339 u8 resp_size; 1340 u8 reserved8; 1341 __le64 resp_addr; 1342 u8 mrw_flags; 1343 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL 1344 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 1345 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL 1346 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL 1347 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL 1348 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL 1349 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL 1350 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 1351 #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL 1352 #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4 1353 u8 unused24[3]; 1354 __le32 key; 1355 }; 1356 1357 /* creq_deallocate_key_resp (size:128b/16B) */ 1358 struct creq_deallocate_key_resp { 1359 u8 type; 1360 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL 1361 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 1362 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL 1363 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 1364 u8 status; 1365 __le16 cookie; 1366 __le32 xid; 1367 u8 v; 1368 #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL 1369 u8 event; 1370 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL 1371 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 1372 __le16 reserved16; 1373 __le32 bound_window_info; 1374 }; 1375 1376 /* cmdq_register_mr (size:448b/56B) */ 1377 struct cmdq_register_mr { 1378 u8 opcode; 1379 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL 1380 #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 1381 u8 cmd_size; 1382 __le16 flags; 1383 #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL 1384 #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID 0x2UL 1385 #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO 0x4UL 1386 __le16 cookie; 1387 u8 resp_size; 1388 u8 reserved8; 1389 __le64 resp_addr; 1390 u8 log2_pg_size_lvl; 1391 #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL 1392 #define CMDQ_REGISTER_MR_LVL_SFT 0 1393 #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL 1394 #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL 1395 #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL 1396 #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 1397 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL 1398 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 1399 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2) 1400 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2) 1401 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2) 1402 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2) 1403 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2) 1404 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2) 1405 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2) 1406 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2) 1407 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G 1408 #define CMDQ_REGISTER_MR_UNUSED1 0x80UL 1409 u8 access; 1410 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL 1411 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL 1412 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL 1413 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL 1414 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL 1415 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL 1416 __le16 log2_pbl_pg_size; 1417 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL 1418 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 1419 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL 1420 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL 1421 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL 1422 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL 1423 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL 1424 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL 1425 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL 1426 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL 1427 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 1428 #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL 1429 #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 1430 __le32 key; 1431 __le64 pbl; 1432 __le64 va; 1433 __le64 mr_size; 1434 __le16 steering_tag; 1435 u8 reserved48[6]; 1436 }; 1437 1438 /* creq_register_mr_resp (size:128b/16B) */ 1439 struct creq_register_mr_resp { 1440 u8 type; 1441 #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL 1442 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 1443 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1444 #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 1445 u8 status; 1446 __le16 cookie; 1447 __le32 xid; 1448 u8 v; 1449 #define CREQ_REGISTER_MR_RESP_V 0x1UL 1450 u8 event; 1451 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL 1452 #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 1453 u8 reserved48[6]; 1454 }; 1455 1456 /* cmdq_deregister_mr (size:192b/24B) */ 1457 struct cmdq_deregister_mr { 1458 u8 opcode; 1459 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL 1460 #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 1461 u8 cmd_size; 1462 __le16 flags; 1463 __le16 cookie; 1464 u8 resp_size; 1465 u8 reserved8; 1466 __le64 resp_addr; 1467 __le32 lkey; 1468 __le32 unused_0; 1469 }; 1470 1471 /* creq_deregister_mr_resp (size:128b/16B) */ 1472 struct creq_deregister_mr_resp { 1473 u8 type; 1474 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL 1475 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 1476 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1477 #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 1478 u8 status; 1479 __le16 cookie; 1480 __le32 xid; 1481 u8 v; 1482 #define CREQ_DEREGISTER_MR_RESP_V 0x1UL 1483 u8 event; 1484 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL 1485 #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 1486 __le16 reserved16; 1487 __le32 bound_windows; 1488 }; 1489 1490 /* cmdq_add_gid (size:384b/48B) */ 1491 struct cmdq_add_gid { 1492 u8 opcode; 1493 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL 1494 #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID 1495 u8 cmd_size; 1496 __le16 flags; 1497 __le16 cookie; 1498 u8 resp_size; 1499 u8 reserved8; 1500 __le64 resp_addr; 1501 __be32 gid[4]; 1502 __be16 src_mac[3]; 1503 __le16 vlan; 1504 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1505 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1506 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL 1507 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 1508 #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL 1509 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 1510 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1511 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1512 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1513 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1514 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1515 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1516 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1517 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1518 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 1519 #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL 1520 __le16 ipid; 1521 __le16 stats_ctx; 1522 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL 1523 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0 1524 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1525 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1526 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1527 __le32 unused_0; 1528 }; 1529 1530 /* creq_add_gid_resp (size:128b/16B) */ 1531 struct creq_add_gid_resp { 1532 u8 type; 1533 #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL 1534 #define CREQ_ADD_GID_RESP_TYPE_SFT 0 1535 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL 1536 #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT 1537 u8 status; 1538 __le16 cookie; 1539 __le32 xid; 1540 u8 v; 1541 #define CREQ_ADD_GID_RESP_V 0x1UL 1542 u8 event; 1543 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL 1544 #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID 1545 u8 reserved48[6]; 1546 }; 1547 1548 /* cmdq_delete_gid (size:192b/24B) */ 1549 struct cmdq_delete_gid { 1550 u8 opcode; 1551 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL 1552 #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID 1553 u8 cmd_size; 1554 __le16 flags; 1555 __le16 cookie; 1556 u8 resp_size; 1557 u8 reserved8; 1558 __le64 resp_addr; 1559 __le16 gid_index; 1560 u8 unused_0[6]; 1561 }; 1562 1563 /* creq_delete_gid_resp (size:128b/16B) */ 1564 struct creq_delete_gid_resp { 1565 u8 type; 1566 #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL 1567 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 1568 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL 1569 #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 1570 u8 status; 1571 __le16 cookie; 1572 __le32 xid; 1573 u8 v; 1574 #define CREQ_DELETE_GID_RESP_V 0x1UL 1575 u8 event; 1576 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL 1577 #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 1578 u8 reserved48[6]; 1579 }; 1580 1581 /* cmdq_modify_gid (size:384b/48B) */ 1582 struct cmdq_modify_gid { 1583 u8 opcode; 1584 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL 1585 #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 1586 u8 cmd_size; 1587 __le16 flags; 1588 __le16 cookie; 1589 u8 resp_size; 1590 u8 reserved8; 1591 __le64 resp_addr; 1592 __be32 gid[4]; 1593 __be16 src_mac[3]; 1594 __le16 vlan; 1595 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL 1596 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 1597 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL 1598 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 1599 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1600 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1601 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1602 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1603 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1604 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1605 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1606 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1607 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 1608 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL 1609 __le16 ipid; 1610 __le16 gid_index; 1611 __le16 stats_ctx; 1612 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1613 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1614 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1615 __le16 unused_0; 1616 }; 1617 1618 /* creq_modify_gid_resp (size:128b/16B) */ 1619 struct creq_modify_gid_resp { 1620 u8 type; 1621 #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL 1622 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 1623 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL 1624 #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 1625 u8 status; 1626 __le16 cookie; 1627 __le32 xid; 1628 u8 v; 1629 #define CREQ_MODIFY_GID_RESP_V 0x1UL 1630 u8 event; 1631 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL 1632 #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 1633 u8 reserved48[6]; 1634 }; 1635 1636 /* cmdq_query_gid (size:192b/24B) */ 1637 struct cmdq_query_gid { 1638 u8 opcode; 1639 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL 1640 #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID 1641 u8 cmd_size; 1642 __le16 flags; 1643 __le16 cookie; 1644 u8 resp_size; 1645 u8 reserved8; 1646 __le64 resp_addr; 1647 __le16 gid_index; 1648 u8 unused16[6]; 1649 }; 1650 1651 /* creq_query_gid_resp (size:128b/16B) */ 1652 struct creq_query_gid_resp { 1653 u8 type; 1654 #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL 1655 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 1656 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL 1657 #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 1658 u8 status; 1659 __le16 cookie; 1660 __le32 size; 1661 u8 v; 1662 #define CREQ_QUERY_GID_RESP_V 0x1UL 1663 u8 event; 1664 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL 1665 #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 1666 u8 reserved48[6]; 1667 }; 1668 1669 /* creq_query_gid_resp_sb (size:320b/40B) */ 1670 struct creq_query_gid_resp_sb { 1671 u8 opcode; 1672 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL 1673 #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 1674 u8 status; 1675 __le16 cookie; 1676 __le16 flags; 1677 u8 resp_size; 1678 u8 reserved8; 1679 __le32 gid[4]; 1680 __le16 src_mac[3]; 1681 __le16 vlan; 1682 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1683 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1684 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL 1685 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 1686 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL 1687 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 1688 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1689 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12) 1690 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12) 1691 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12) 1692 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12) 1693 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1694 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1695 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1696 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 1697 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL 1698 __le16 ipid; 1699 __le16 gid_index; 1700 __le32 unused_0; 1701 }; 1702 1703 /* cmdq_create_qp1 (size:640b/80B) */ 1704 struct cmdq_create_qp1 { 1705 u8 opcode; 1706 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL 1707 #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 1708 u8 cmd_size; 1709 __le16 flags; 1710 __le16 cookie; 1711 u8 resp_size; 1712 u8 reserved8; 1713 __le64 resp_addr; 1714 __le64 qp_handle; 1715 __le32 qp_flags; 1716 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL 1717 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL 1718 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1719 #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 1720 u8 type; 1721 #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL 1722 #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI 1723 u8 sq_pg_size_sq_lvl; 1724 #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL 1725 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 1726 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL 1727 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL 1728 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL 1729 #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2 1730 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL 1731 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 1732 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1733 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1734 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1735 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1736 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1737 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1738 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G 1739 u8 rq_pg_size_rq_lvl; 1740 #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL 1741 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 1742 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL 1743 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL 1744 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL 1745 #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2 1746 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL 1747 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 1748 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1749 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1750 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1751 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1752 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1753 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1754 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G 1755 u8 unused_0; 1756 __le32 dpi; 1757 __le32 sq_size; 1758 __le32 rq_size; 1759 __le16 sq_fwo_sq_sge; 1760 #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL 1761 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 1762 #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL 1763 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 1764 __le16 rq_fwo_rq_sge; 1765 #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL 1766 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 1767 #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL 1768 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 1769 __le32 scq_cid; 1770 __le32 rcq_cid; 1771 __le32 srq_cid; 1772 __le32 pd_id; 1773 __le64 sq_pbl; 1774 __le64 rq_pbl; 1775 }; 1776 1777 /* creq_create_qp1_resp (size:128b/16B) */ 1778 struct creq_create_qp1_resp { 1779 u8 type; 1780 #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL 1781 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 1782 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL 1783 #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 1784 u8 status; 1785 __le16 cookie; 1786 __le32 xid; 1787 u8 v; 1788 #define CREQ_CREATE_QP1_RESP_V 0x1UL 1789 u8 event; 1790 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL 1791 #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 1792 u8 reserved48[6]; 1793 }; 1794 1795 /* cmdq_destroy_qp1 (size:192b/24B) */ 1796 struct cmdq_destroy_qp1 { 1797 u8 opcode; 1798 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL 1799 #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 1800 u8 cmd_size; 1801 __le16 flags; 1802 __le16 cookie; 1803 u8 resp_size; 1804 u8 reserved8; 1805 __le64 resp_addr; 1806 __le32 qp1_cid; 1807 __le32 unused_0; 1808 }; 1809 1810 /* creq_destroy_qp1_resp (size:128b/16B) */ 1811 struct creq_destroy_qp1_resp { 1812 u8 type; 1813 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL 1814 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 1815 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL 1816 #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 1817 u8 status; 1818 __le16 cookie; 1819 __le32 xid; 1820 u8 v; 1821 #define CREQ_DESTROY_QP1_RESP_V 0x1UL 1822 u8 event; 1823 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL 1824 #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 1825 u8 reserved48[6]; 1826 }; 1827 1828 /* cmdq_create_ah (size:512b/64B) */ 1829 struct cmdq_create_ah { 1830 u8 opcode; 1831 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL 1832 #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH 1833 u8 cmd_size; 1834 __le16 flags; 1835 __le16 cookie; 1836 u8 resp_size; 1837 u8 reserved8; 1838 __le64 resp_addr; 1839 __le64 ah_handle; 1840 __le32 dgid[4]; 1841 u8 type; 1842 #define CMDQ_CREATE_AH_TYPE_V1 0x0UL 1843 #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL 1844 #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL 1845 #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6 1846 u8 hop_limit; 1847 __le16 sgid_index; 1848 __le32 dest_vlan_id_flow_label; 1849 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL 1850 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 1851 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL 1852 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 1853 __le32 pd_id; 1854 __le32 unused_0; 1855 __le16 dest_mac[3]; 1856 u8 traffic_class; 1857 u8 enable_cc; 1858 #define CMDQ_CREATE_AH_ENABLE_CC 0x1UL 1859 }; 1860 1861 /* creq_create_ah_resp (size:128b/16B) */ 1862 struct creq_create_ah_resp { 1863 u8 type; 1864 #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL 1865 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 1866 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL 1867 #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 1868 u8 status; 1869 __le16 cookie; 1870 __le32 xid; 1871 u8 v; 1872 #define CREQ_CREATE_AH_RESP_V 0x1UL 1873 u8 event; 1874 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL 1875 #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 1876 u8 reserved48[6]; 1877 }; 1878 1879 /* cmdq_destroy_ah (size:192b/24B) */ 1880 struct cmdq_destroy_ah { 1881 u8 opcode; 1882 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL 1883 #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 1884 u8 cmd_size; 1885 __le16 flags; 1886 __le16 cookie; 1887 u8 resp_size; 1888 u8 reserved8; 1889 __le64 resp_addr; 1890 __le32 ah_cid; 1891 __le32 unused_0; 1892 }; 1893 1894 /* creq_destroy_ah_resp (size:128b/16B) */ 1895 struct creq_destroy_ah_resp { 1896 u8 type; 1897 #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL 1898 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 1899 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL 1900 #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 1901 u8 status; 1902 __le16 cookie; 1903 __le32 xid; 1904 u8 v; 1905 #define CREQ_DESTROY_AH_RESP_V 0x1UL 1906 u8 event; 1907 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL 1908 #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 1909 u8 reserved48[6]; 1910 }; 1911 1912 /* cmdq_query_roce_stats (size:192b/24B) */ 1913 struct cmdq_query_roce_stats { 1914 u8 opcode; 1915 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL 1916 #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 1917 u8 cmd_size; 1918 __le16 flags; 1919 #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL 1920 #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL 1921 __le16 cookie; 1922 u8 resp_size; 1923 u8 collection_id; 1924 __le64 resp_addr; 1925 __le32 function_id; 1926 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL 1927 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0 1928 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL 1929 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8 1930 #define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL 1931 __le32 reserved32; 1932 }; 1933 1934 /* creq_query_roce_stats_resp (size:128b/16B) */ 1935 struct creq_query_roce_stats_resp { 1936 u8 type; 1937 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL 1938 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 1939 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL 1940 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 1941 u8 status; 1942 __le16 cookie; 1943 __le32 size; 1944 u8 v; 1945 #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL 1946 u8 event; 1947 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL 1948 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \ 1949 CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 1950 u8 reserved48[6]; 1951 }; 1952 1953 /* creq_query_roce_stats_resp_sb (size:2944b/368B) */ 1954 struct creq_query_roce_stats_resp_sb { 1955 u8 opcode; 1956 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL 1957 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \ 1958 CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 1959 u8 status; 1960 __le16 cookie; 1961 __le16 flags; 1962 u8 resp_size; 1963 u8 rsvd; 1964 __le32 num_counters; 1965 __le32 rsvd1; 1966 __le64 to_retransmits; 1967 __le64 seq_err_naks_rcvd; 1968 __le64 max_retry_exceeded; 1969 __le64 rnr_naks_rcvd; 1970 __le64 missing_resp; 1971 __le64 unrecoverable_err; 1972 __le64 bad_resp_err; 1973 __le64 local_qp_op_err; 1974 __le64 local_protection_err; 1975 __le64 mem_mgmt_op_err; 1976 __le64 remote_invalid_req_err; 1977 __le64 remote_access_err; 1978 __le64 remote_op_err; 1979 __le64 dup_req; 1980 __le64 res_exceed_max; 1981 __le64 res_length_mismatch; 1982 __le64 res_exceeds_wqe; 1983 __le64 res_opcode_err; 1984 __le64 res_rx_invalid_rkey; 1985 __le64 res_rx_domain_err; 1986 __le64 res_rx_no_perm; 1987 __le64 res_rx_range_err; 1988 __le64 res_tx_invalid_rkey; 1989 __le64 res_tx_domain_err; 1990 __le64 res_tx_no_perm; 1991 __le64 res_tx_range_err; 1992 __le64 res_irrq_oflow; 1993 __le64 res_unsup_opcode; 1994 __le64 res_unaligned_atomic; 1995 __le64 res_rem_inv_err; 1996 __le64 res_mem_error; 1997 __le64 res_srq_err; 1998 __le64 res_cmp_err; 1999 __le64 res_invalid_dup_rkey; 2000 __le64 res_wqe_format_err; 2001 __le64 res_cq_load_err; 2002 __le64 res_srq_load_err; 2003 __le64 res_tx_pci_err; 2004 __le64 res_rx_pci_err; 2005 __le64 res_oos_drop_count; 2006 __le64 active_qp_count_p0; 2007 __le64 active_qp_count_p1; 2008 __le64 active_qp_count_p2; 2009 __le64 active_qp_count_p3; 2010 }; 2011 2012 /* cmdq_query_roce_stats_ext (size:192b/24B) */ 2013 struct cmdq_query_roce_stats_ext { 2014 u8 opcode; 2015 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL 2016 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST \ 2017 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 2018 u8 cmd_size; 2019 __le16 flags; 2020 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL 2021 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL 2022 __le16 cookie; 2023 u8 resp_size; 2024 u8 collection_id; 2025 __le64 resp_addr; 2026 __le32 function_id; 2027 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL 2028 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0 2029 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL 2030 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8 2031 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL 2032 __le32 reserved32; 2033 }; 2034 2035 /* creq_query_roce_stats_ext_resp (size:128b/16B) */ 2036 struct creq_query_roce_stats_ext_resp { 2037 u8 type; 2038 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL 2039 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0 2040 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL 2041 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST \ 2042 CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 2043 u8 status; 2044 __le16 cookie; 2045 __le32 size; 2046 u8 v; 2047 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL 2048 u8 event; 2049 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL 2050 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST \ 2051 CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 2052 u8 reserved48[6]; 2053 }; 2054 2055 /* creq_query_roce_stats_ext_resp_sb (size:1856b/232B) */ 2056 struct creq_query_roce_stats_ext_resp_sb { 2057 u8 opcode; 2058 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 2059 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST \ 2060 CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 2061 u8 status; 2062 __le16 cookie; 2063 __le16 flags; 2064 u8 resp_size; 2065 u8 rsvd; 2066 __le64 tx_atomic_req_pkts; 2067 __le64 tx_read_req_pkts; 2068 __le64 tx_read_res_pkts; 2069 __le64 tx_write_req_pkts; 2070 __le64 tx_send_req_pkts; 2071 __le64 tx_roce_pkts; 2072 __le64 tx_roce_bytes; 2073 __le64 rx_atomic_req_pkts; 2074 __le64 rx_read_req_pkts; 2075 __le64 rx_read_res_pkts; 2076 __le64 rx_write_req_pkts; 2077 __le64 rx_send_req_pkts; 2078 __le64 rx_roce_pkts; 2079 __le64 rx_roce_bytes; 2080 __le64 rx_roce_good_pkts; 2081 __le64 rx_roce_good_bytes; 2082 __le64 rx_out_of_buffer_pkts; 2083 __le64 rx_out_of_sequence_pkts; 2084 __le64 tx_cnp_pkts; 2085 __le64 rx_cnp_pkts; 2086 __le64 rx_ecn_marked_pkts; 2087 __le64 tx_cnp_bytes; 2088 __le64 rx_cnp_bytes; 2089 __le64 seq_err_naks_rcvd; 2090 __le64 rnr_naks_rcvd; 2091 __le64 missing_resp; 2092 __le64 to_retransmit; 2093 __le64 dup_req; 2094 }; 2095 2096 /* cmdq_query_func (size:128b/16B) */ 2097 struct cmdq_query_func { 2098 u8 opcode; 2099 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL 2100 #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 2101 u8 cmd_size; 2102 __le16 flags; 2103 __le16 cookie; 2104 u8 resp_size; 2105 u8 reserved8; 2106 __le64 resp_addr; 2107 }; 2108 2109 /* creq_query_func_resp (size:128b/16B) */ 2110 struct creq_query_func_resp { 2111 u8 type; 2112 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL 2113 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 2114 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2115 #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 2116 u8 status; 2117 __le16 cookie; 2118 __le32 size; 2119 u8 v; 2120 #define CREQ_QUERY_FUNC_RESP_V 0x1UL 2121 u8 event; 2122 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL 2123 #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 2124 u8 reserved48[6]; 2125 }; 2126 2127 /* creq_query_func_resp_sb (size:1088b/136B) */ 2128 struct creq_query_func_resp_sb { 2129 u8 opcode; 2130 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL 2131 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 2132 u8 status; 2133 __le16 cookie; 2134 __le16 flags; 2135 u8 resp_size; 2136 u8 reserved8; 2137 __le64 max_mr_size; 2138 __le32 max_qp; 2139 __le16 max_qp_wr; 2140 __le16 dev_cap_flags; 2141 #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL 2142 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL 2143 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 2144 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1) 2145 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1) 2146 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1) 2147 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST \ 2148 CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT 2149 #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL 2150 #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL 2151 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL 2152 #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL 2153 #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL 2154 #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL 2155 #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL 2156 __le32 max_cq; 2157 __le32 max_cqe; 2158 __le32 max_pd; 2159 u8 max_sge; 2160 u8 max_srq_sge; 2161 u8 max_qp_rd_atom; 2162 u8 max_qp_init_rd_atom; 2163 __le32 max_mr; 2164 __le32 max_mw; 2165 __le32 max_raw_eth_qp; 2166 __le32 max_ah; 2167 __le32 max_fmr; 2168 __le32 max_srq_wr; 2169 __le32 max_pkeys; 2170 __le32 max_inline_data; 2171 u8 max_map_per_fmr; 2172 u8 l2_db_space_size; 2173 __le16 max_srq; 2174 __le32 max_gid; 2175 __le32 tqm_alloc_reqs[12]; 2176 __le32 max_dpi; 2177 u8 max_sge_var_wqe; 2178 u8 dev_cap_ext_flags; 2179 #define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED 0x1UL 2180 #define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED 0x2UL 2181 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED 0x4UL 2182 #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED 0x8UL 2183 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED 0x10UL 2184 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED 0x20UL 2185 #define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED 0x40UL 2186 #define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED 0x80UL 2187 __le16 max_inline_data_var_wqe; 2188 __le32 start_qid; 2189 u8 max_msn_table_size; 2190 u8 reserved8_1; 2191 __le16 dev_cap_ext_flags_2; 2192 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED 0x1UL 2193 #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED 0x2UL 2194 #define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED 0x4UL 2195 #define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED 0x8UL 2196 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK 0x30UL 2197 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4 2198 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (0x0UL << 4) 2199 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (0x1UL << 4) 2200 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (0x2UL << 4) 2201 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST \ 2202 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE 2203 __le16 max_xp_qp_size; 2204 __le16 create_qp_batch_size; 2205 __le16 destroy_qp_batch_size; 2206 __le16 reserved16; 2207 __le64 reserved64; 2208 }; 2209 2210 /* cmdq_set_func_resources (size:448b/56B) */ 2211 struct cmdq_set_func_resources { 2212 u8 opcode; 2213 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL 2214 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST\ 2215 CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 2216 u8 cmd_size; 2217 __le16 flags; 2218 #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 2219 __le16 cookie; 2220 u8 resp_size; 2221 u8 reserved8; 2222 __le64 resp_addr; 2223 __le32 number_of_qp; 2224 __le32 number_of_mrw; 2225 __le32 number_of_srq; 2226 __le32 number_of_cq; 2227 __le32 max_qp_per_vf; 2228 __le32 max_mrw_per_vf; 2229 __le32 max_srq_per_vf; 2230 __le32 max_cq_per_vf; 2231 __le32 max_gid_per_vf; 2232 __le32 stat_ctx_id; 2233 }; 2234 2235 /* creq_set_func_resources_resp (size:128b/16B) */ 2236 struct creq_set_func_resources_resp { 2237 u8 type; 2238 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL 2239 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 2240 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL 2241 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 2242 u8 status; 2243 __le16 cookie; 2244 __le32 reserved32; 2245 u8 v; 2246 #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL 2247 u8 event; 2248 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL 2249 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \ 2250 CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 2251 u8 reserved48[6]; 2252 }; 2253 2254 /* cmdq_map_tc_to_cos (size:192b/24B) */ 2255 struct cmdq_map_tc_to_cos { 2256 u8 opcode; 2257 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL 2258 #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 2259 u8 cmd_size; 2260 __le16 flags; 2261 __le16 cookie; 2262 u8 resp_size; 2263 u8 reserved8; 2264 __le64 resp_addr; 2265 __le16 cos0; 2266 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL 2267 #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 2268 __le16 cos1; 2269 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL 2270 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL 2271 #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 2272 __le32 unused_0; 2273 }; 2274 2275 /* creq_map_tc_to_cos_resp (size:128b/16B) */ 2276 struct creq_map_tc_to_cos_resp { 2277 u8 type; 2278 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL 2279 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 2280 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL 2281 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 2282 u8 status; 2283 __le16 cookie; 2284 __le32 reserved32; 2285 u8 v; 2286 #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL 2287 u8 event; 2288 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL 2289 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 2290 u8 reserved48[6]; 2291 }; 2292 2293 /* cmdq_query_roce_cc (size:128b/16B) */ 2294 struct cmdq_query_roce_cc { 2295 u8 opcode; 2296 #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL 2297 #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 2298 u8 cmd_size; 2299 __le16 flags; 2300 __le16 cookie; 2301 u8 resp_size; 2302 u8 reserved8; 2303 __le64 resp_addr; 2304 }; 2305 2306 /* creq_query_roce_cc_resp (size:128b/16B) */ 2307 struct creq_query_roce_cc_resp { 2308 u8 type; 2309 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2310 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0 2311 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2312 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 2313 u8 status; 2314 __le16 cookie; 2315 __le32 size; 2316 u8 v; 2317 #define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL 2318 u8 event; 2319 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL 2320 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 2321 u8 reserved48[6]; 2322 }; 2323 2324 /* creq_query_roce_cc_resp_sb (size:256b/32B) */ 2325 struct creq_query_roce_cc_resp_sb { 2326 u8 opcode; 2327 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL 2328 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST \ 2329 CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 2330 u8 status; 2331 __le16 cookie; 2332 __le16 flags; 2333 u8 resp_size; 2334 u8 reserved8; 2335 u8 enable_cc; 2336 #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL 2337 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL 2338 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1 2339 u8 tos_dscp_tos_ecn; 2340 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL 2341 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0 2342 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL 2343 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2 2344 u8 g; 2345 u8 num_phases_per_state; 2346 __le16 init_cr; 2347 __le16 init_tr; 2348 u8 alt_vlan_pcp; 2349 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL 2350 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0 2351 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL 2352 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3 2353 u8 alt_tos_dscp; 2354 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL 2355 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0 2356 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL 2357 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6 2358 u8 cc_mode; 2359 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL 2360 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL 2361 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST \ 2362 CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 2363 u8 tx_queue; 2364 __le16 rtt; 2365 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL 2366 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0 2367 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL 2368 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14 2369 __le16 tcp_cp; 2370 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL 2371 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0 2372 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL 2373 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10 2374 __le16 inactivity_th; 2375 u8 pkts_per_phase; 2376 u8 time_per_phase; 2377 __le32 reserved32; 2378 }; 2379 2380 /* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */ 2381 struct creq_query_roce_cc_resp_sb_tlv { 2382 __le16 cmd_discr; 2383 u8 reserved_8b; 2384 u8 tlv_flags; 2385 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2386 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2387 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2388 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2389 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2390 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2391 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 2392 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2393 __le16 tlv_type; 2394 __le16 length; 2395 u8 total_size; 2396 u8 reserved56[7]; 2397 u8 opcode; 2398 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL 2399 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST \ 2400 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 2401 u8 status; 2402 __le16 cookie; 2403 __le16 flags; 2404 u8 resp_size; 2405 u8 reserved8; 2406 u8 enable_cc; 2407 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL 2408 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL 2409 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1 2410 u8 tos_dscp_tos_ecn; 2411 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL 2412 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0 2413 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL 2414 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2 2415 u8 g; 2416 u8 num_phases_per_state; 2417 __le16 init_cr; 2418 __le16 init_tr; 2419 u8 alt_vlan_pcp; 2420 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL 2421 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0 2422 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL 2423 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3 2424 u8 alt_tos_dscp; 2425 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2426 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0 2427 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL 2428 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6 2429 u8 cc_mode; 2430 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL 2431 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL 2432 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST\ 2433 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 2434 u8 tx_queue; 2435 __le16 rtt; 2436 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL 2437 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0 2438 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL 2439 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14 2440 __le16 tcp_cp; 2441 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL 2442 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0 2443 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL 2444 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10 2445 __le16 inactivity_th; 2446 u8 pkts_per_phase; 2447 u8 time_per_phase; 2448 __le32 reserved32; 2449 }; 2450 2451 /* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */ 2452 struct creq_query_roce_cc_gen1_resp_sb_tlv { 2453 __le16 cmd_discr; 2454 u8 reserved_8b; 2455 u8 tlv_flags; 2456 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2457 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2458 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2459 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2460 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2461 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2462 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 2463 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2464 __le16 tlv_type; 2465 __le16 length; 2466 __le64 reserved64; 2467 __le16 inactivity_th_hi; 2468 __le16 min_time_between_cnps; 2469 __le16 init_cp; 2470 u8 tr_update_mode; 2471 u8 tr_update_cycles; 2472 u8 fr_num_rtts; 2473 u8 ai_rate_increase; 2474 __le16 reduction_relax_rtts_th; 2475 __le16 additional_relax_cr_th; 2476 __le16 cr_min_th; 2477 u8 bw_avg_weight; 2478 u8 actual_cr_factor; 2479 __le16 max_cp_cr_th; 2480 u8 cp_bias_en; 2481 u8 cp_bias; 2482 u8 cnp_ecn; 2483 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL 2484 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL 2485 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL 2486 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST \ 2487 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 2488 u8 rtt_jitter_en; 2489 __le16 link_bytes_per_usec; 2490 __le16 reset_cc_cr_th; 2491 u8 cr_width; 2492 u8 quota_period_min; 2493 u8 quota_period_max; 2494 u8 quota_period_abs_max; 2495 __le16 tr_lower_bound; 2496 u8 cr_prob_factor; 2497 u8 tr_prob_factor; 2498 __le16 fairness_cr_th; 2499 u8 red_div; 2500 u8 cnp_ratio_th; 2501 __le16 exp_ai_rtts; 2502 u8 exp_ai_cr_cp_ratio; 2503 u8 use_rate_table; 2504 __le16 cp_exp_update_th; 2505 __le16 high_exp_ai_rtts_th1; 2506 __le16 high_exp_ai_rtts_th2; 2507 __le16 actual_cr_cong_free_rtts_th; 2508 __le16 severe_cong_cr_th1; 2509 __le16 severe_cong_cr_th2; 2510 __le32 link64B_per_rtt; 2511 u8 cc_ack_bytes; 2512 u8 reduce_init_en; 2513 __le16 reduce_init_cong_free_rtts_th; 2514 u8 random_no_red_en; 2515 u8 actual_cr_shift_correction_en; 2516 u8 quota_period_adjust_en; 2517 u8 reserved[5]; 2518 }; 2519 2520 /* cmdq_modify_roce_cc (size:448b/56B) */ 2521 struct cmdq_modify_roce_cc { 2522 u8 opcode; 2523 #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL 2524 #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 2525 u8 cmd_size; 2526 __le16 flags; 2527 __le16 cookie; 2528 u8 resp_size; 2529 u8 reserved8; 2530 __le64 resp_addr; 2531 __le32 modify_mask; 2532 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL 2533 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL 2534 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2535 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL 2536 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL 2537 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL 2538 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL 2539 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2540 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2541 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL 2542 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL 2543 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL 2544 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL 2545 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2546 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2547 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2548 u8 enable_cc; 2549 #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL 2550 #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL 2551 #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1 2552 u8 g; 2553 u8 num_phases_per_state; 2554 u8 pkts_per_phase; 2555 __le16 init_cr; 2556 __le16 init_tr; 2557 u8 tos_dscp_tos_ecn; 2558 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL 2559 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0 2560 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL 2561 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2 2562 u8 alt_vlan_pcp; 2563 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL 2564 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0 2565 #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL 2566 #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3 2567 __le16 alt_tos_dscp; 2568 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL 2569 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0 2570 #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL 2571 #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6 2572 __le16 rtt; 2573 #define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL 2574 #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0 2575 #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL 2576 #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14 2577 __le16 tcp_cp; 2578 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL 2579 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0 2580 #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL 2581 #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10 2582 u8 cc_mode; 2583 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL 2584 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2585 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 2586 u8 tx_queue; 2587 __le16 inactivity_th; 2588 u8 time_per_phase; 2589 u8 reserved8_1; 2590 __le16 reserved16; 2591 __le32 reserved32; 2592 __le64 reserved64; 2593 }; 2594 2595 /* cmdq_modify_roce_cc_tlv (size:640b/80B) */ 2596 struct cmdq_modify_roce_cc_tlv { 2597 __le16 cmd_discr; 2598 u8 reserved_8b; 2599 u8 tlv_flags; 2600 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL 2601 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2602 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2603 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL 2604 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2605 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2606 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST \ 2607 CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES 2608 __le16 tlv_type; 2609 __le16 length; 2610 u8 total_size; 2611 u8 reserved56[7]; 2612 u8 opcode; 2613 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL 2614 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 2615 u8 cmd_size; 2616 __le16 flags; 2617 __le16 cookie; 2618 u8 resp_size; 2619 u8 reserved8; 2620 __le64 resp_addr; 2621 __le32 modify_mask; 2622 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL 2623 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL 2624 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2625 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL 2626 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL 2627 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL 2628 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL 2629 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2630 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2631 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL 2632 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL 2633 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL 2634 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL 2635 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2636 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2637 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2638 u8 enable_cc; 2639 #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL 2640 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL 2641 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1 2642 u8 g; 2643 u8 num_phases_per_state; 2644 u8 pkts_per_phase; 2645 __le16 init_cr; 2646 __le16 init_tr; 2647 u8 tos_dscp_tos_ecn; 2648 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL 2649 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0 2650 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL 2651 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2 2652 u8 alt_vlan_pcp; 2653 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL 2654 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0 2655 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL 2656 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3 2657 __le16 alt_tos_dscp; 2658 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2659 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0 2660 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL 2661 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6 2662 __le16 rtt; 2663 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL 2664 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0 2665 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL 2666 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14 2667 __le16 tcp_cp; 2668 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL 2669 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0 2670 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL 2671 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10 2672 u8 cc_mode; 2673 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL 2674 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2675 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST\ 2676 CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 2677 u8 tx_queue; 2678 __le16 inactivity_th; 2679 u8 time_per_phase; 2680 u8 reserved8_1; 2681 __le16 reserved16; 2682 __le32 reserved32; 2683 __le64 reserved64; 2684 __le64 reservedtlvpad; 2685 }; 2686 2687 /* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */ 2688 struct cmdq_modify_roce_cc_gen1_tlv { 2689 __le16 cmd_discr; 2690 u8 reserved_8b; 2691 u8 tlv_flags; 2692 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL 2693 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2694 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2695 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL 2696 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2697 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2698 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST\ 2699 CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES 2700 __le16 tlv_type; 2701 __le16 length; 2702 __le64 reserved64; 2703 __le64 modify_mask; 2704 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL 2705 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL 2706 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL 2707 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL 2708 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL 2709 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL 2710 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL 2711 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL 2712 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL 2713 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL 2714 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL 2715 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL 2716 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL 2717 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL 2718 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL 2719 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL 2720 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL 2721 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL 2722 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL 2723 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL 2724 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL 2725 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL 2726 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL 2727 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL 2728 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL 2729 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL 2730 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL 2731 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL 2732 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL 2733 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL 2734 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL 2735 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL 2736 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL 2737 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL 2738 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL 2739 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL 2740 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL 2741 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL 2742 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL 2743 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL 2744 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH \ 2745 0x10000000000ULL 2746 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL 2747 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN \ 2748 0x40000000000ULL 2749 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL 2750 __le16 inactivity_th_hi; 2751 __le16 min_time_between_cnps; 2752 __le16 init_cp; 2753 u8 tr_update_mode; 2754 u8 tr_update_cycles; 2755 u8 fr_num_rtts; 2756 u8 ai_rate_increase; 2757 __le16 reduction_relax_rtts_th; 2758 __le16 additional_relax_cr_th; 2759 __le16 cr_min_th; 2760 u8 bw_avg_weight; 2761 u8 actual_cr_factor; 2762 __le16 max_cp_cr_th; 2763 u8 cp_bias_en; 2764 u8 cp_bias; 2765 u8 cnp_ecn; 2766 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL 2767 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL 2768 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL 2769 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 2770 u8 rtt_jitter_en; 2771 __le16 link_bytes_per_usec; 2772 __le16 reset_cc_cr_th; 2773 u8 cr_width; 2774 u8 quota_period_min; 2775 u8 quota_period_max; 2776 u8 quota_period_abs_max; 2777 __le16 tr_lower_bound; 2778 u8 cr_prob_factor; 2779 u8 tr_prob_factor; 2780 __le16 fairness_cr_th; 2781 u8 red_div; 2782 u8 cnp_ratio_th; 2783 __le16 exp_ai_rtts; 2784 u8 exp_ai_cr_cp_ratio; 2785 u8 use_rate_table; 2786 __le16 cp_exp_update_th; 2787 __le16 high_exp_ai_rtts_th1; 2788 __le16 high_exp_ai_rtts_th2; 2789 __le16 actual_cr_cong_free_rtts_th; 2790 __le16 severe_cong_cr_th1; 2791 __le16 severe_cong_cr_th2; 2792 __le32 link64B_per_rtt; 2793 u8 cc_ack_bytes; 2794 u8 reduce_init_en; 2795 __le16 reduce_init_cong_free_rtts_th; 2796 u8 random_no_red_en; 2797 u8 actual_cr_shift_correction_en; 2798 u8 quota_period_adjust_en; 2799 u8 reserved[5]; 2800 }; 2801 2802 /* creq_modify_roce_cc_resp (size:128b/16B) */ 2803 struct creq_modify_roce_cc_resp { 2804 u8 type; 2805 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2806 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0 2807 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2808 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 2809 u8 status; 2810 __le16 cookie; 2811 __le32 reserved32; 2812 u8 v; 2813 #define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL 2814 u8 event; 2815 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL 2816 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 2817 u8 reserved48[6]; 2818 }; 2819 2820 /* cmdq_set_link_aggr_mode_cc (size:320b/40B) */ 2821 struct cmdq_set_link_aggr_mode_cc { 2822 u8 opcode; 2823 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 2824 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST \ 2825 CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 2826 u8 cmd_size; 2827 __le16 flags; 2828 __le16 cookie; 2829 u8 resp_size; 2830 u8 reserved8; 2831 __le64 resp_addr; 2832 __le32 modify_mask; 2833 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL 2834 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL 2835 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL 2836 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL 2837 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL 2838 u8 aggr_enable; 2839 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL 2840 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL 2841 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1 2842 u8 active_port_map; 2843 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL 2844 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0 2845 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL 2846 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4 2847 u8 member_port_map; 2848 u8 link_aggr_mode; 2849 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL 2850 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL 2851 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL 2852 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL 2853 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 2854 __le16 stat_ctx_id[4]; 2855 __le64 rsvd1; 2856 }; 2857 2858 /* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */ 2859 struct creq_set_link_aggr_mode_resources_resp { 2860 u8 type; 2861 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL 2862 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0 2863 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL 2864 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 2865 u8 status; 2866 __le16 cookie; 2867 __le32 reserved32; 2868 u8 v; 2869 #define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL 2870 u8 event; 2871 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL 2872 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST\ 2873 CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 2874 u8 reserved48[6]; 2875 }; 2876 2877 /* creq_func_event (size:128b/16B) */ 2878 struct creq_func_event { 2879 u8 type; 2880 #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL 2881 #define CREQ_FUNC_EVENT_TYPE_SFT 0 2882 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL 2883 #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 2884 u8 reserved56[7]; 2885 u8 v; 2886 #define CREQ_FUNC_EVENT_V 0x1UL 2887 u8 event; 2888 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL 2889 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL 2890 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL 2891 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL 2892 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL 2893 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL 2894 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL 2895 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL 2896 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL 2897 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL 2898 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL 2899 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL 2900 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL 2901 #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 2902 u8 reserved48[6]; 2903 }; 2904 2905 /* creq_qp_event (size:128b/16B) */ 2906 struct creq_qp_event { 2907 u8 type; 2908 #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL 2909 #define CREQ_QP_EVENT_TYPE_SFT 0 2910 #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL 2911 #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT 2912 u8 status; 2913 #define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL 2914 #define CREQ_QP_EVENT_STATUS_FAIL 0x1UL 2915 #define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL 2916 #define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL 2917 #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL 2918 #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL 2919 #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL 2920 #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL 2921 #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 2922 __le16 cookie; 2923 __le32 reserved32; 2924 u8 v; 2925 #define CREQ_QP_EVENT_V 0x1UL 2926 u8 event; 2927 #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL 2928 #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL 2929 #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL 2930 #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL 2931 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL 2932 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL 2933 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL 2934 #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL 2935 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL 2936 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL 2937 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL 2938 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL 2939 #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL 2940 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL 2941 #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL 2942 #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL 2943 #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL 2944 #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL 2945 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL 2946 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL 2947 #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL 2948 #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL 2949 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL 2950 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL 2951 #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL 2952 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL 2953 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL 2954 #define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL 2955 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL 2956 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL 2957 #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL 2958 #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL 2959 #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL 2960 #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL 2961 #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL 2962 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 2963 #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 2964 #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 2965 u8 reserved48[6]; 2966 }; 2967 2968 /* creq_qp_error_notification (size:128b/16B) */ 2969 struct creq_qp_error_notification { 2970 u8 type; 2971 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 2972 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 2973 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL 2974 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 2975 u8 status; 2976 u8 req_slow_path_state; 2977 u8 req_err_state_reason; 2978 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR 0X0UL 2979 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR 0X1UL 2980 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT 0X2UL 2981 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT 0X3UL 2982 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 0X4UL 2983 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 0X5UL 2984 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 0X6UL 2985 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 0X7UL 2986 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR 0X8UL 2987 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR 0X9UL 2988 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH 0XAUL 2989 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP 0XBUL 2990 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND 0XCUL 2991 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG 0XDUL 2992 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE 0XEUL 2993 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR 0XFUL 2994 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR 0X10UL 2995 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR 0X11UL 2996 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR 0X12UL 2997 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR 0X13UL 2998 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR 0X14UL 2999 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR 0X15UL 3000 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR 0X16UL 3001 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR 0X17UL 3002 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR 0X18UL 3003 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR 0X19UL 3004 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR 0X1AUL 3005 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR 0X1BUL 3006 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR 0X1CUL 3007 __le32 xid; 3008 u8 v; 3009 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL 3010 u8 event; 3011 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 3012 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST \ 3013 CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 3014 u8 res_slow_path_state; 3015 u8 res_err_state_reason; 3016 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR 0x0UL 3017 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX 0x1UL 3018 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH 0x2UL 3019 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE 0x3UL 3020 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR 0x4UL 3021 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT 0x5UL 3022 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY 0x6UL 3023 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR 0x7UL 3024 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION 0x8UL 3025 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR 0x9UL 3026 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY 0xaUL 3027 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR 0xbUL 3028 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION 0xcUL 3029 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR 0xdUL 3030 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW 0xeUL 3031 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE 0xfUL 3032 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC 0x10UL 3033 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE 0x11UL 3034 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR 0x12UL 3035 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR 0x13UL 3036 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR 0x14UL 3037 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY 0x15UL 3038 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR 0x16UL 3039 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR 0x17UL 3040 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR 0x18UL 3041 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR 0x19UL 3042 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR 0x1bUL 3043 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR 0x1cUL 3044 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND 0x1dUL 3045 __le16 sq_cons_idx; 3046 __le16 rq_cons_idx; 3047 }; 3048 3049 /* creq_cq_error_notification (size:128b/16B) */ 3050 struct creq_cq_error_notification { 3051 u8 type; 3052 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 3053 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0 3054 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL 3055 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 3056 u8 status; 3057 u8 cq_err_reason; 3058 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL 3059 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL 3060 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL 3061 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL 3062 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL 3063 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL 3064 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST \ 3065 CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 3066 u8 reserved8; 3067 __le32 xid; 3068 u8 v; 3069 #define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL 3070 u8 event; 3071 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 3072 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST \ 3073 CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 3074 u8 reserved48[6]; 3075 }; 3076 3077 /* sq_base (size:64b/8B) */ 3078 struct sq_base { 3079 u8 wqe_type; 3080 #define SQ_BASE_WQE_TYPE_SEND 0x0UL 3081 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3082 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL 3083 #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL 3084 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3085 #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL 3086 #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL 3087 #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL 3088 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL 3089 #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL 3090 #define SQ_BASE_WQE_TYPE_BIND 0xeUL 3091 #define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL 3092 #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR 3093 u8 unused_0[7]; 3094 }; 3095 3096 /* sq_sge (size:128b/16B) */ 3097 struct sq_sge { 3098 __le64 va_or_pa; 3099 __le32 l_key; 3100 __le32 size; 3101 }; 3102 3103 /* sq_psn_search (size:64b/8B) */ 3104 struct sq_psn_search { 3105 __le32 opcode_start_psn; 3106 #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL 3107 #define SQ_PSN_SEARCH_START_PSN_SFT 0 3108 #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL 3109 #define SQ_PSN_SEARCH_OPCODE_SFT 24 3110 __le32 flags_next_psn; 3111 #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL 3112 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 3113 #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL 3114 #define SQ_PSN_SEARCH_FLAGS_SFT 24 3115 }; 3116 3117 /* sq_psn_search_ext (size:128b/16B) */ 3118 struct sq_psn_search_ext { 3119 __le32 opcode_start_psn; 3120 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL 3121 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 3122 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL 3123 #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 3124 __le32 flags_next_psn; 3125 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL 3126 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 3127 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL 3128 #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 3129 __le16 start_slot_idx; 3130 __le16 reserved16; 3131 __le32 reserved32; 3132 }; 3133 3134 /* sq_msn_search (size:64b/8B) */ 3135 struct sq_msn_search { 3136 __le64 start_idx_next_psn_start_psn; 3137 #define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL 3138 #define SQ_MSN_SEARCH_START_PSN_SFT 0 3139 #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL 3140 #define SQ_MSN_SEARCH_NEXT_PSN_SFT 24 3141 #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL 3142 #define SQ_MSN_SEARCH_START_IDX_SFT 48 3143 }; 3144 3145 /* sq_send (size:1024b/128B) */ 3146 struct sq_send { 3147 u8 wqe_type; 3148 #define SQ_SEND_WQE_TYPE_SEND 0x0UL 3149 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3150 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL 3151 #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID 3152 u8 flags; 3153 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3154 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3155 #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL 3156 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3157 #define SQ_SEND_FLAGS_UC_FENCE 0x4UL 3158 #define SQ_SEND_FLAGS_SE 0x8UL 3159 #define SQ_SEND_FLAGS_INLINE 0x10UL 3160 #define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL 3161 #define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL 3162 u8 wqe_size; 3163 u8 reserved8_1; 3164 __le32 inv_key_or_imm_data; 3165 __le32 length; 3166 __le32 q_key; 3167 __le32 dst_qp; 3168 #define SQ_SEND_DST_QP_MASK 0xffffffUL 3169 #define SQ_SEND_DST_QP_SFT 0 3170 __le32 avid; 3171 #define SQ_SEND_AVID_MASK 0xfffffUL 3172 #define SQ_SEND_AVID_SFT 0 3173 __le32 reserved32; 3174 __le32 timestamp; 3175 #define SQ_SEND_TIMESTAMP_MASK 0xffffffUL 3176 #define SQ_SEND_TIMESTAMP_SFT 0 3177 __le32 data[24]; 3178 }; 3179 3180 /* sq_send_hdr (size:256b/32B) */ 3181 struct sq_send_hdr { 3182 u8 wqe_type; 3183 #define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL 3184 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3185 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL 3186 #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 3187 u8 flags; 3188 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3189 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3190 #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3191 #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3192 #define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL 3193 #define SQ_SEND_HDR_FLAGS_SE 0x8UL 3194 #define SQ_SEND_HDR_FLAGS_INLINE 0x10UL 3195 #define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL 3196 #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3197 u8 wqe_size; 3198 u8 reserved8_1; 3199 __le32 inv_key_or_imm_data; 3200 __le32 length; 3201 __le32 q_key; 3202 __le32 dst_qp; 3203 #define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL 3204 #define SQ_SEND_HDR_DST_QP_SFT 0 3205 __le32 avid; 3206 #define SQ_SEND_HDR_AVID_MASK 0xfffffUL 3207 #define SQ_SEND_HDR_AVID_SFT 0 3208 __le32 reserved32; 3209 __le32 timestamp; 3210 #define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL 3211 #define SQ_SEND_HDR_TIMESTAMP_SFT 0 3212 }; 3213 3214 /* sq_send_raweth_qp1 (size:1024b/128B) */ 3215 struct sq_send_raweth_qp1 { 3216 u8 wqe_type; 3217 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL 3218 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 3219 u8 flags; 3220 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK \ 3221 0xffUL 3222 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT \ 3223 0 3224 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL 3225 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3226 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL 3227 #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL 3228 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL 3229 #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL 3230 #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL 3231 u8 wqe_size; 3232 u8 reserved8; 3233 __le16 lflags; 3234 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3235 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL 3236 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL 3237 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL 3238 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL 3239 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL 3240 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL 3241 __le16 cfa_action; 3242 __le32 length; 3243 __le32 reserved32_1; 3244 __le32 cfa_meta; 3245 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL 3246 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 3247 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL 3248 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL 3249 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 3250 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL 3251 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 3252 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 3253 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 3254 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 3255 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 3256 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 3257 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 3258 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST\ 3259 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG 3260 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 3261 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 3262 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL 3263 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 3264 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28) 3265 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 3266 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG 3267 __le32 reserved32_2; 3268 __le32 reserved32_3; 3269 __le32 timestamp; 3270 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL 3271 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0 3272 __le32 data[24]; 3273 }; 3274 3275 /* sq_send_raweth_qp1_hdr (size:256b/32B) */ 3276 struct sq_send_raweth_qp1_hdr { 3277 u8 wqe_type; 3278 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL 3279 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 3280 u8 flags; 3281 #define \ 3282 SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3283 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3284 0 3285 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL 3286 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3287 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL 3288 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL 3289 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL 3290 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL 3291 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL 3292 u8 wqe_size; 3293 u8 reserved8; 3294 __le16 lflags; 3295 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3296 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL 3297 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL 3298 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL 3299 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL 3300 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL 3301 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL 3302 __le16 cfa_action; 3303 __le32 length; 3304 __le32 reserved32_1; 3305 __le32 cfa_meta; 3306 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL 3307 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0 3308 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL 3309 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL 3310 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13 3311 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL 3312 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16 3313 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 3314 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 3315 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 3316 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 3317 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 3318 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 3319 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST\ 3320 SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG 3321 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 3322 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19 3323 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL 3324 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28 3325 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28) 3326 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 3327 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST\ 3328 SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG 3329 __le32 reserved32_2; 3330 __le32 reserved32_3; 3331 __le32 timestamp; 3332 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL 3333 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0 3334 }; 3335 3336 /* sq_rdma (size:1024b/128B) */ 3337 struct sq_rdma { 3338 u8 wqe_type; 3339 #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL 3340 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3341 #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL 3342 #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE 3343 u8 flags; 3344 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3345 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3346 #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL 3347 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3348 #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL 3349 #define SQ_RDMA_FLAGS_SE 0x8UL 3350 #define SQ_RDMA_FLAGS_INLINE 0x10UL 3351 #define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL 3352 #define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL 3353 u8 wqe_size; 3354 u8 reserved8; 3355 __le32 imm_data; 3356 __le32 length; 3357 __le32 reserved32_1; 3358 __le64 remote_va; 3359 __le32 remote_key; 3360 __le32 timestamp; 3361 #define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL 3362 #define SQ_RDMA_TIMESTAMP_SFT 0 3363 __le32 data[24]; 3364 }; 3365 3366 /* sq_rdma_hdr (size:256b/32B) */ 3367 struct sq_rdma_hdr { 3368 u8 wqe_type; 3369 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL 3370 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3371 #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL 3372 #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE 3373 u8 flags; 3374 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3375 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3376 #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL 3377 #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3378 #define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL 3379 #define SQ_RDMA_HDR_FLAGS_SE 0x8UL 3380 #define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL 3381 #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL 3382 #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL 3383 u8 wqe_size; 3384 u8 reserved8; 3385 __le32 imm_data; 3386 __le32 length; 3387 __le32 reserved32_1; 3388 __le64 remote_va; 3389 __le32 remote_key; 3390 __le32 timestamp; 3391 #define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL 3392 #define SQ_RDMA_HDR_TIMESTAMP_SFT 0 3393 }; 3394 3395 /* sq_atomic (size:1024b/128B) */ 3396 struct sq_atomic { 3397 u8 wqe_type; 3398 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL 3399 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL 3400 #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 3401 u8 flags; 3402 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3403 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3404 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL 3405 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3406 #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL 3407 #define SQ_ATOMIC_FLAGS_SE 0x8UL 3408 #define SQ_ATOMIC_FLAGS_INLINE 0x10UL 3409 #define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL 3410 #define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL 3411 __le16 reserved16; 3412 __le32 remote_key; 3413 __le64 remote_va; 3414 __le64 swap_data; 3415 __le64 cmp_data; 3416 __le32 data[24]; 3417 }; 3418 3419 /* sq_atomic_hdr (size:256b/32B) */ 3420 struct sq_atomic_hdr { 3421 u8 wqe_type; 3422 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL 3423 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL 3424 #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 3425 u8 flags; 3426 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3427 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3428 #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL 3429 #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3430 #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL 3431 #define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL 3432 #define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL 3433 #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL 3434 #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL 3435 __le16 reserved16; 3436 __le32 remote_key; 3437 __le64 remote_va; 3438 __le64 swap_data; 3439 __le64 cmp_data; 3440 }; 3441 3442 /* sq_localinvalidate (size:1024b/128B) */ 3443 struct sq_localinvalidate { 3444 u8 wqe_type; 3445 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL 3446 #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 3447 u8 flags; 3448 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK\ 3449 0xffUL 3450 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3451 0 3452 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL 3453 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3454 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL 3455 #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL 3456 #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL 3457 #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL 3458 #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL 3459 __le16 reserved16; 3460 __le32 inv_l_key; 3461 __le64 reserved64; 3462 u8 reserved128[16]; 3463 __le32 data[24]; 3464 }; 3465 3466 /* sq_localinvalidate_hdr (size:256b/32B) */ 3467 struct sq_localinvalidate_hdr { 3468 u8 wqe_type; 3469 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL 3470 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 3471 u8 flags; 3472 #define \ 3473 SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3474 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3475 0 3476 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL 3477 #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3478 #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL 3479 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL 3480 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL 3481 #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL 3482 #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL 3483 __le16 reserved16; 3484 __le32 inv_l_key; 3485 __le64 reserved64; 3486 u8 reserved128[16]; 3487 }; 3488 3489 /* sq_fr_pmr (size:1024b/128B) */ 3490 struct sq_fr_pmr { 3491 u8 wqe_type; 3492 #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL 3493 #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR 3494 u8 flags; 3495 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL 3496 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3497 #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL 3498 #define SQ_FR_PMR_FLAGS_SE 0x8UL 3499 #define SQ_FR_PMR_FLAGS_INLINE 0x10UL 3500 #define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL 3501 #define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL 3502 u8 access_cntl; 3503 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3504 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL 3505 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3506 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3507 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3508 u8 zero_based_page_size_log; 3509 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL 3510 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 3511 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3512 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3513 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3514 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3515 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3516 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3517 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3518 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3519 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3520 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3521 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3522 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3523 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3524 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3525 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3526 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3527 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3528 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3529 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3530 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3531 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3532 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3533 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3534 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3535 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3536 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3537 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3538 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3539 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3540 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3541 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3542 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3543 #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 3544 #define SQ_FR_PMR_ZERO_BASED 0x20UL 3545 __le32 l_key; 3546 u8 length[5]; 3547 u8 reserved8_1; 3548 u8 reserved8_2; 3549 u8 numlevels_pbl_page_size_log; 3550 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 3551 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 3552 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3553 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3554 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3555 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3556 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3557 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3558 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3559 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3560 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3561 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3562 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3563 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3564 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3565 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3566 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3567 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3568 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3569 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3570 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3571 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3572 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3573 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3574 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3575 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3576 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3577 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3578 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3579 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3580 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3581 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3582 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3583 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3584 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 3585 #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL 3586 #define SQ_FR_PMR_NUMLEVELS_SFT 6 3587 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6) 3588 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6) 3589 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6) 3590 #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2 3591 __le64 pblptr; 3592 __le64 va; 3593 __le32 data[24]; 3594 }; 3595 3596 /* sq_fr_pmr_hdr (size:256b/32B) */ 3597 struct sq_fr_pmr_hdr { 3598 u8 wqe_type; 3599 #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL 3600 #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 3601 u8 flags; 3602 #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL 3603 #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3604 #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL 3605 #define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL 3606 #define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL 3607 #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL 3608 #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL 3609 u8 access_cntl; 3610 #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3611 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 3612 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3613 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3614 #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3615 u8 zero_based_page_size_log; 3616 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL 3617 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0 3618 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3619 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3620 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3621 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3622 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3623 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3624 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3625 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3626 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3627 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3628 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3629 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3630 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3631 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3632 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3633 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3634 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3635 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3636 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3637 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3638 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3639 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3640 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3641 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3642 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3643 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3644 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3645 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3646 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3647 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3648 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3649 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3650 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 3651 #define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL 3652 __le32 l_key; 3653 u8 length[5]; 3654 u8 reserved8_1; 3655 u8 reserved8_2; 3656 u8 numlevels_pbl_page_size_log; 3657 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 3658 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 3659 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3660 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3661 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3662 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3663 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3664 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3665 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3666 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3667 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3668 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3669 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3670 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3671 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3672 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3673 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3674 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3675 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3676 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3677 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3678 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3679 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3680 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3681 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3682 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3683 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3684 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3685 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3686 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3687 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3688 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3689 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3690 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3691 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 3692 #define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL 3693 #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6 3694 #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6) 3695 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6) 3696 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6) 3697 #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 3698 __le64 pblptr; 3699 __le64 va; 3700 }; 3701 3702 /* sq_bind (size:1024b/128B) */ 3703 struct sq_bind { 3704 u8 wqe_type; 3705 #define SQ_BIND_WQE_TYPE_BIND 0xeUL 3706 #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND 3707 u8 flags; 3708 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3709 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3710 #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL 3711 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3712 #define SQ_BIND_FLAGS_UC_FENCE 0x4UL 3713 #define SQ_BIND_FLAGS_SE 0x8UL 3714 #define SQ_BIND_FLAGS_INLINE 0x10UL 3715 #define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL 3716 #define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL 3717 u8 access_cntl; 3718 #define \ 3719 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\ 3720 0xffUL 3721 #define \ 3722 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 3723 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3724 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL 3725 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3726 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3727 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL 3728 u8 reserved8_1; 3729 u8 mw_type_zero_based; 3730 #define SQ_BIND_ZERO_BASED 0x1UL 3731 #define SQ_BIND_MW_TYPE 0x2UL 3732 #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1) 3733 #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1) 3734 #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2 3735 u8 reserved8_2; 3736 __le16 reserved16; 3737 __le32 parent_l_key; 3738 __le32 l_key; 3739 __le64 va; 3740 u8 length[5]; 3741 u8 reserved24[3]; 3742 __le32 data[24]; 3743 }; 3744 3745 /* sq_bind_hdr (size:256b/32B) */ 3746 struct sq_bind_hdr { 3747 u8 wqe_type; 3748 #define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL 3749 #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND 3750 u8 flags; 3751 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3752 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3753 #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3754 #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3755 #define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL 3756 #define SQ_BIND_HDR_FLAGS_SE 0x8UL 3757 #define SQ_BIND_HDR_FLAGS_INLINE 0x10UL 3758 #define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL 3759 #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3760 u8 access_cntl; 3761 #define \ 3762 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\ 3763 0xffUL 3764 #define \ 3765 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT \ 3766 0 3767 #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3768 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 3769 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3770 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3771 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3772 u8 reserved8_1; 3773 u8 mw_type_zero_based; 3774 #define SQ_BIND_HDR_ZERO_BASED 0x1UL 3775 #define SQ_BIND_HDR_MW_TYPE 0x2UL 3776 #define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1) 3777 #define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1) 3778 #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2 3779 u8 reserved8_2; 3780 __le16 reserved16; 3781 __le32 parent_l_key; 3782 __le32 l_key; 3783 __le64 va; 3784 u8 length[5]; 3785 u8 reserved24[3]; 3786 }; 3787 3788 /* rq_wqe (size:1024b/128B) */ 3789 struct rq_wqe { 3790 u8 wqe_type; 3791 #define RQ_WQE_WQE_TYPE_RCV 0x80UL 3792 #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV 3793 u8 flags; 3794 u8 wqe_size; 3795 u8 reserved8; 3796 __le32 reserved32; 3797 __le32 wr_id[2]; 3798 #define RQ_WQE_WR_ID_MASK 0xfffffUL 3799 #define RQ_WQE_WR_ID_SFT 0 3800 u8 reserved128[16]; 3801 __le32 data[24]; 3802 }; 3803 3804 /* rq_wqe_hdr (size:256b/32B) */ 3805 struct rq_wqe_hdr { 3806 u8 wqe_type; 3807 #define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL 3808 #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV 3809 u8 flags; 3810 u8 wqe_size; 3811 u8 reserved8; 3812 __le32 reserved32; 3813 __le32 wr_id[2]; 3814 #define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL 3815 #define RQ_WQE_HDR_WR_ID_SFT 0 3816 u8 reserved128[16]; 3817 }; 3818 3819 /* cq_base (size:256b/32B) */ 3820 struct cq_base { 3821 __le64 reserved64_1; 3822 __le64 reserved64_2; 3823 __le64 reserved64_3; 3824 u8 cqe_type_toggle; 3825 #define CQ_BASE_TOGGLE 0x1UL 3826 #define CQ_BASE_CQE_TYPE_MASK 0x1eUL 3827 #define CQ_BASE_CQE_TYPE_SFT 1 3828 #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1) 3829 #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1) 3830 #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1) 3831 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 3832 #define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 3833 #define CQ_BASE_CQE_TYPE_REQ_V3 (0x8UL << 1) 3834 #define CQ_BASE_CQE_TYPE_RES_RC_V3 (0x9UL << 1) 3835 #define CQ_BASE_CQE_TYPE_RES_UD_V3 (0xaUL << 1) 3836 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1) 3837 #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1) 3838 #define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1) 3839 #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1) 3840 #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1) 3841 #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF 3842 u8 status; 3843 #define CQ_BASE_STATUS_OK 0x0UL 3844 #define CQ_BASE_STATUS_BAD_RESPONSE_ERR 0x1UL 3845 #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR 0x2UL 3846 #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL 3847 #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3848 #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR 0x5UL 3849 #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR 0x6UL 3850 #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL 3851 #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL 3852 #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR 0x9UL 3853 #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR 0xaUL 3854 #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL 3855 #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL 3856 #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 3857 #define CQ_BASE_STATUS_HW_FLUSH_ERR 0xeUL 3858 #define CQ_BASE_STATUS_OVERFLOW_ERR 0xfUL 3859 #define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR 3860 __le16 reserved16; 3861 __le32 opaque; 3862 }; 3863 3864 /* cq_req (size:256b/32B) */ 3865 struct cq_req { 3866 __le64 qp_handle; 3867 __le16 sq_cons_idx; 3868 __le16 reserved16_1; 3869 __le32 reserved32_2; 3870 __le64 reserved64; 3871 u8 cqe_type_toggle; 3872 #define CQ_REQ_TOGGLE 0x1UL 3873 #define CQ_REQ_CQE_TYPE_MASK 0x1eUL 3874 #define CQ_REQ_CQE_TYPE_SFT 1 3875 #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1) 3876 #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ 3877 #define CQ_REQ_PUSH 0x20UL 3878 u8 status; 3879 #define CQ_REQ_STATUS_OK 0x0UL 3880 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL 3881 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL 3882 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL 3883 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL 3884 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3885 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 3886 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL 3887 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL 3888 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL 3889 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL 3890 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL 3891 #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 3892 __le16 reserved16_2; 3893 __le32 reserved32_1; 3894 }; 3895 3896 /* cq_res_rc (size:256b/32B) */ 3897 struct cq_res_rc { 3898 __le32 length; 3899 __le32 imm_data_or_inv_r_key; 3900 __le64 qp_handle; 3901 __le64 mr_handle; 3902 u8 cqe_type_toggle; 3903 #define CQ_RES_RC_TOGGLE 0x1UL 3904 #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL 3905 #define CQ_RES_RC_CQE_TYPE_SFT 1 3906 #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1) 3907 #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC 3908 u8 status; 3909 #define CQ_RES_RC_STATUS_OK 0x0UL 3910 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3911 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL 3912 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3913 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3914 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3915 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 3916 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3917 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL 3918 #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR 3919 __le16 flags; 3920 #define CQ_RES_RC_FLAGS_SRQ 0x1UL 3921 #define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL 3922 #define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL 3923 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ 3924 #define CQ_RES_RC_FLAGS_IMM 0x2UL 3925 #define CQ_RES_RC_FLAGS_INV 0x4UL 3926 #define CQ_RES_RC_FLAGS_RDMA 0x8UL 3927 #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3) 3928 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3) 3929 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE 3930 __le32 srq_or_rq_wr_id; 3931 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3932 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 3933 }; 3934 3935 /* cq_res_ud (size:256b/32B) */ 3936 struct cq_res_ud { 3937 __le16 length; 3938 #define CQ_RES_UD_LENGTH_MASK 0x3fffUL 3939 #define CQ_RES_UD_LENGTH_SFT 0 3940 __le16 cfa_metadata; 3941 #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL 3942 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 3943 #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL 3944 #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL 3945 #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 3946 __le32 imm_data; 3947 __le64 qp_handle; 3948 __le16 src_mac[3]; 3949 __le16 src_qp_low; 3950 u8 cqe_type_toggle; 3951 #define CQ_RES_UD_TOGGLE 0x1UL 3952 #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL 3953 #define CQ_RES_UD_CQE_TYPE_SFT 1 3954 #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1) 3955 #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD 3956 u8 status; 3957 #define CQ_RES_UD_STATUS_OK 0x0UL 3958 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL 3959 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 3960 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL 3961 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3962 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3963 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 3964 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL 3965 #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR 3966 __le16 flags; 3967 #define CQ_RES_UD_FLAGS_SRQ 0x1UL 3968 #define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL 3969 #define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL 3970 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ 3971 #define CQ_RES_UD_FLAGS_IMM 0x2UL 3972 #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL 3973 #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 3974 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL 3975 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 3976 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 3977 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 3978 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 3979 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 3980 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL 3981 #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 3982 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6) 3983 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 3984 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 3985 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 3986 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 3987 #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET 3988 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 3989 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 3990 __le32 src_qp_high_srq_or_rq_wr_id; 3991 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 3992 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 3993 #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL 3994 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 3995 }; 3996 3997 /* cq_res_ud_v2 (size:256b/32B) */ 3998 struct cq_res_ud_v2 { 3999 __le16 length; 4000 #define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL 4001 #define CQ_RES_UD_V2_LENGTH_SFT 0 4002 __le16 cfa_metadata0; 4003 #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL 4004 #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0 4005 #define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL 4006 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4007 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13 4008 __le32 imm_data; 4009 __le64 qp_handle; 4010 __le16 src_mac[3]; 4011 __le16 src_qp_low; 4012 u8 cqe_type_toggle; 4013 #define CQ_RES_UD_V2_TOGGLE 0x1UL 4014 #define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL 4015 #define CQ_RES_UD_V2_CQE_TYPE_SFT 1 4016 #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1) 4017 #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD 4018 u8 status; 4019 #define CQ_RES_UD_V2_STATUS_OK 0x0UL 4020 #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4021 #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4022 #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4023 #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4024 #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4025 #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4026 #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL 4027 #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 4028 __le16 flags; 4029 #define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL 4030 #define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL 4031 #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL 4032 #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ 4033 #define CQ_RES_UD_V2_FLAGS_IMM 0x2UL 4034 #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL 4035 #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2 4036 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 4037 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4 4038 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4039 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4040 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4041 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 4042 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 4043 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6 4044 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4045 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 4046 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4047 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4048 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4049 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET 4050 __le32 src_qp_high_srq_or_rq_wr_id; 4051 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4052 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0 4053 #define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL 4054 #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20 4055 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4056 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20 4057 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4058 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4059 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4060 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4061 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4062 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4063 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4064 #define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL 4065 #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL 4066 #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24 4067 }; 4068 4069 /* cq_res_ud_cfa (size:256b/32B) */ 4070 struct cq_res_ud_cfa { 4071 __le16 length; 4072 #define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL 4073 #define CQ_RES_UD_CFA_LENGTH_SFT 0 4074 __le16 cfa_code; 4075 __le32 imm_data; 4076 __le32 qid; 4077 #define CQ_RES_UD_CFA_QID_MASK 0xfffffUL 4078 #define CQ_RES_UD_CFA_QID_SFT 0 4079 __le32 cfa_metadata; 4080 #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL 4081 #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0 4082 #define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL 4083 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL 4084 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13 4085 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL 4086 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16 4087 __le16 src_mac[3]; 4088 __le16 src_qp_low; 4089 u8 cqe_type_toggle; 4090 #define CQ_RES_UD_CFA_TOGGLE 0x1UL 4091 #define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL 4092 #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1 4093 #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 4094 #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA 4095 u8 status; 4096 #define CQ_RES_UD_CFA_STATUS_OK 0x0UL 4097 #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4098 #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4099 #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4100 #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4101 #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4102 #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4103 #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL 4104 #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 4105 __le16 flags; 4106 #define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL 4107 #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL 4108 #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL 4109 #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 4110 #define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL 4111 #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL 4112 #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2 4113 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL 4114 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4 4115 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4116 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4117 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4118 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 4119 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL 4120 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6 4121 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4122 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 4123 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4124 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4125 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4126 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET 4127 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 4128 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10 4129 __le32 src_qp_high_srq_or_rq_wr_id; 4130 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4131 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0 4132 #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL 4133 #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24 4134 }; 4135 4136 /* cq_res_ud_cfa_v2 (size:256b/32B) */ 4137 struct cq_res_ud_cfa_v2 { 4138 __le16 length; 4139 #define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL 4140 #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0 4141 __le16 cfa_metadata0; 4142 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL 4143 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0 4144 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL 4145 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4146 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13 4147 __le32 imm_data; 4148 __le32 qid; 4149 #define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL 4150 #define CQ_RES_UD_CFA_V2_QID_SFT 0 4151 __le32 cfa_metadata2; 4152 __le16 src_mac[3]; 4153 __le16 src_qp_low; 4154 u8 cqe_type_toggle; 4155 #define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL 4156 #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL 4157 #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1 4158 #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 4159 #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA 4160 u8 status; 4161 #define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL 4162 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4163 #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4164 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4165 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4166 #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4167 #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4168 #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL 4169 #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 4170 __le16 flags; 4171 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL 4172 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL 4173 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL 4174 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 4175 #define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL 4176 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL 4177 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2 4178 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 4179 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4 4180 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4181 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4182 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4183 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 4184 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 4185 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6 4186 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4187 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 4188 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4189 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4190 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4191 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST \ 4192 CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET 4193 __le32 src_qp_high_srq_or_rq_wr_id; 4194 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4195 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0 4196 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL 4197 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20 4198 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4199 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20 4200 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4201 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4202 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4203 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4204 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4205 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4206 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST \ 4207 CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4208 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL 4209 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL 4210 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24 4211 }; 4212 4213 /* cq_res_raweth_qp1 (size:256b/32B) */ 4214 struct cq_res_raweth_qp1 { 4215 __le16 length; 4216 #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL 4217 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 4218 __le16 raweth_qp1_flags; 4219 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL 4220 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 4221 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL 4222 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 4223 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 4224 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 4225 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 4226 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 4227 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 4228 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 4229 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 4230 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 4231 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 4232 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 4233 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \ 4234 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 4235 __le16 raweth_qp1_errors; 4236 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 4237 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 4238 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 4239 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 4240 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 4241 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 4242 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 4243 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 4244 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 4245 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 4246 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 4247 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 4248 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 4249 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 4250 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 4251 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 4252 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 4253 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 4254 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 4255 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 4256 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 4257 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 4258 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 4259 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 4260 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 4261 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12) 4262 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12) 4263 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 4264 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 4265 __le16 raweth_qp1_cfa_code; 4266 __le64 qp_handle; 4267 __le32 raweth_qp1_flags2; 4268 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL 4269 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL 4270 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL 4271 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL 4272 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 4273 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 4274 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 4275 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4) 4276 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 4277 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 4278 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 4279 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \ 4280 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 4281 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 4282 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 4283 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL 4284 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10 4285 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 4286 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 4287 __le32 raweth_qp1_metadata; 4288 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL 4289 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0 4290 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL 4291 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 4292 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL 4293 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL 4294 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 4295 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL 4296 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 4297 u8 cqe_type_toggle; 4298 #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL 4299 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL 4300 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 4301 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 4302 #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 4303 u8 status; 4304 #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL 4305 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4306 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4307 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4308 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4309 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4310 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4311 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL 4312 #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 4313 __le16 flags; 4314 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL 4315 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL 4316 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL 4317 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 4318 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 4319 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4320 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 4321 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 4322 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 4323 }; 4324 4325 /* cq_res_raweth_qp1_v2 (size:256b/32B) */ 4326 struct cq_res_raweth_qp1_v2 { 4327 __le16 length; 4328 #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL 4329 #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0 4330 __le16 raweth_qp1_flags; 4331 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL 4332 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0 4333 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL 4334 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 4335 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6 4336 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 4337 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 4338 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 4339 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 4340 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 4341 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 4342 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 4343 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 4344 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 4345 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST \ 4346 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 4347 __le16 raweth_qp1_errors; 4348 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 4349 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 4350 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 4351 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 4352 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 4353 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 4354 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 4355 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 4356 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 4357 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 4358 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 4359 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 4360 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 4361 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 4362 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 4363 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 4364 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 4365 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 4366 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 4367 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 4368 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 4369 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 4370 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 4371 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 4372 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 4373 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ 4374 (0x7UL << 12) 4375 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ 4376 (0x8UL << 12) 4377 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 4378 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 4379 __le16 cfa_metadata0; 4380 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL 4381 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0 4382 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL 4383 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4384 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13 4385 __le64 qp_handle; 4386 __le32 raweth_qp1_flags2; 4387 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL 4388 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 4389 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 4390 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 4391 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4) 4392 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 4393 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 4394 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 4395 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \ 4396 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 4397 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 4398 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 4399 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL 4400 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10 4401 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 4402 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 4403 __le32 cfa_metadata2; 4404 u8 cqe_type_toggle; 4405 #define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL 4406 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL 4407 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1 4408 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 4409 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 4410 u8 status; 4411 #define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL 4412 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4413 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4414 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4415 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4416 #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4417 #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4418 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL 4419 #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 4420 __le16 flags; 4421 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL 4422 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL 4423 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL 4424 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 4425 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 4426 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4427 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0 4428 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL 4429 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20 4430 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4431 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20 4432 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4433 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4434 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4435 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4436 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4437 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4438 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST \ 4439 CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4440 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL 4441 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 4442 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 4443 }; 4444 4445 /* cq_terminal (size:256b/32B) */ 4446 struct cq_terminal { 4447 __le64 qp_handle; 4448 __le16 sq_cons_idx; 4449 __le16 rq_cons_idx; 4450 __le32 reserved32_1; 4451 __le64 reserved64_3; 4452 u8 cqe_type_toggle; 4453 #define CQ_TERMINAL_TOGGLE 0x1UL 4454 #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL 4455 #define CQ_TERMINAL_CQE_TYPE_SFT 1 4456 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1) 4457 #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL 4458 u8 status; 4459 #define CQ_TERMINAL_STATUS_OK 0x0UL 4460 #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK 4461 __le16 reserved16; 4462 __le32 reserved32_2; 4463 }; 4464 4465 /* cq_cutoff (size:256b/32B) */ 4466 struct cq_cutoff { 4467 __le64 reserved64_1; 4468 __le64 reserved64_2; 4469 __le64 reserved64_3; 4470 u8 cqe_type_toggle; 4471 #define CQ_CUTOFF_TOGGLE 0x1UL 4472 #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL 4473 #define CQ_CUTOFF_CQE_TYPE_SFT 1 4474 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1) 4475 #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF 4476 #define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL 4477 #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5 4478 u8 status; 4479 #define CQ_CUTOFF_STATUS_OK 0x0UL 4480 #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK 4481 __le16 reserved16; 4482 __le32 reserved32; 4483 }; 4484 4485 /* nq_base (size:128b/16B) */ 4486 struct nq_base { 4487 __le16 info10_type; 4488 #define NQ_BASE_TYPE_MASK 0x3fUL 4489 #define NQ_BASE_TYPE_SFT 0 4490 #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL 4491 #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL 4492 #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL 4493 #define NQ_BASE_TYPE_QP_EVENT 0x38UL 4494 #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL 4495 #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT 4496 #define NQ_BASE_INFO10_MASK 0xffc0UL 4497 #define NQ_BASE_INFO10_SFT 6 4498 __le16 info16; 4499 __le32 info32; 4500 __le32 info63_v[2]; 4501 #define NQ_BASE_V 0x1UL 4502 #define NQ_BASE_INFO63_MASK 0xfffffffeUL 4503 #define NQ_BASE_INFO63_SFT 1 4504 }; 4505 4506 /* nq_cn (size:128b/16B) */ 4507 struct nq_cn { 4508 __le16 type; 4509 #define NQ_CN_TYPE_MASK 0x3fUL 4510 #define NQ_CN_TYPE_SFT 0 4511 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 4512 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION 4513 #define NQ_CN_TOGGLE_MASK 0xc0UL 4514 #define NQ_CN_TOGGLE_SFT 6 4515 __le16 reserved16; 4516 __le32 cq_handle_low; 4517 __le32 v; 4518 #define NQ_CN_V 0x1UL 4519 __le32 cq_handle_high; 4520 }; 4521 4522 /* nq_srq_event (size:128b/16B) */ 4523 struct nq_srq_event { 4524 u8 type; 4525 #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL 4526 #define NQ_SRQ_EVENT_TYPE_SFT 0 4527 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL 4528 #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT 4529 #define NQ_SRQ_EVENT_TOGGLE_MASK 0xc0UL 4530 #define NQ_SRQ_EVENT_TOGGLE_SFT 6 4531 u8 event; 4532 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL 4533 #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 4534 __le16 reserved16; 4535 __le32 srq_handle_low; 4536 __le32 v; 4537 #define NQ_SRQ_EVENT_V 0x1UL 4538 __le32 srq_handle_high; 4539 }; 4540 4541 /* nq_dbq_event (size:128b/16B) */ 4542 struct nq_dbq_event { 4543 u8 type; 4544 #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL 4545 #define NQ_DBQ_EVENT_TYPE_SFT 0 4546 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL 4547 #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT 4548 u8 event; 4549 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL 4550 #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 4551 __le16 db_pfid; 4552 #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL 4553 #define NQ_DBQ_EVENT_DB_PFID_SFT 0 4554 __le32 db_dpi; 4555 #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL 4556 #define NQ_DBQ_EVENT_DB_DPI_SFT 0 4557 __le32 v; 4558 #define NQ_DBQ_EVENT_V 0x1UL 4559 __le32 db_type_db_xid; 4560 #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL 4561 #define NQ_DBQ_EVENT_DB_XID_SFT 0 4562 #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL 4563 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 4564 }; 4565 4566 /* xrrq_irrq (size:256b/32B) */ 4567 struct xrrq_irrq { 4568 __le16 credits_type; 4569 #define XRRQ_IRRQ_TYPE 0x1UL 4570 #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL 4571 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL 4572 #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ 4573 #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL 4574 #define XRRQ_IRRQ_CREDITS_SFT 11 4575 __le16 reserved16; 4576 __le32 reserved32; 4577 __le32 psn; 4578 #define XRRQ_IRRQ_PSN_MASK 0xffffffUL 4579 #define XRRQ_IRRQ_PSN_SFT 0 4580 __le32 msn; 4581 #define XRRQ_IRRQ_MSN_MASK 0xffffffUL 4582 #define XRRQ_IRRQ_MSN_SFT 0 4583 __le64 va_or_atomic_result; 4584 __le32 rdma_r_key; 4585 __le32 length; 4586 }; 4587 4588 /* xrrq_orrq (size:256b/32B) */ 4589 struct xrrq_orrq { 4590 __le16 num_sges_type; 4591 #define XRRQ_ORRQ_TYPE 0x1UL 4592 #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL 4593 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL 4594 #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ 4595 #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL 4596 #define XRRQ_ORRQ_NUM_SGES_SFT 11 4597 __le16 reserved16; 4598 __le32 length; 4599 __le32 psn; 4600 #define XRRQ_ORRQ_PSN_MASK 0xffffffUL 4601 #define XRRQ_ORRQ_PSN_SFT 0 4602 __le32 end_psn; 4603 #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL 4604 #define XRRQ_ORRQ_END_PSN_SFT 0 4605 __le64 first_sge_phy_or_sing_sge_va; 4606 __le32 single_sge_l_key; 4607 __le32 single_sge_size; 4608 }; 4609 4610 /* ptu_pte (size:64b/8B) */ 4611 struct ptu_pte { 4612 __le32 page_next_to_last_last_valid[2]; 4613 #define PTU_PTE_VALID 0x1UL 4614 #define PTU_PTE_LAST 0x2UL 4615 #define PTU_PTE_NEXT_TO_LAST 0x4UL 4616 #define PTU_PTE_UNUSED_MASK 0xff8UL 4617 #define PTU_PTE_UNUSED_SFT 3 4618 #define PTU_PTE_PAGE_MASK 0xfffff000UL 4619 #define PTU_PTE_PAGE_SFT 12 4620 }; 4621 4622 /* ptu_pde (size:64b/8B) */ 4623 struct ptu_pde { 4624 __le32 page_valid[2]; 4625 #define PTU_PDE_VALID 0x1UL 4626 #define PTU_PDE_UNUSED_MASK 0xffeUL 4627 #define PTU_PDE_UNUSED_SFT 1 4628 #define PTU_PDE_PAGE_MASK 0xfffff000UL 4629 #define PTU_PDE_PAGE_SFT 12 4630 }; 4631 4632 #endif /* ___BNXT_RE_HSI_H__ */ 4633