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Searched refs:DCCG_AUDIO_DTO0_PHASE (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_audio.h38 SR(DCCG_AUDIO_DTO0_PHASE),\
55 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
72 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
92 uint32_t DCCG_AUDIO_DTO0_PHASE; member
110 uint8_t DCCG_AUDIO_DTO0_PHASE; member
130 uint32_t DCCG_AUDIO_DTO0_PHASE; member
H A Ddce_audio.c1111 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, in dce_aud_wall_dto_setup()
1112 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); in dce_aud_wall_dto_setup()
1203 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, in dce60_aud_wall_dto_setup()
1204 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); in dce60_aud_wall_dto_setup()
/linux/drivers/gpu/drm/radeon/
H A Ddce3_1_afmt.c158 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); in dce3_2_audio_set_dto()
H A Ddce6_afmt.c285 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); in dce6_hdmi_audio_set_dto()
H A Devergreen_hdmi.c268 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); in dce4_hdmi_audio_set_dto()
H A Dr600_hdmi.c331 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); in r600_hdmi_audio_set_dto()
H A Dsid.h913 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 macro
H A Devergreend.h500 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 macro
H A Dr600d.h953 #define DCCG_AUDIO_DTO0_PHASE 0x0514 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h916 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h232 SR_ARR(DCCG_AUDIO_DTO0_PHASE, id), SR_ARR(DCCG_AUDIO_DTO1_MODULE, id), \