Searched refs:DG1_DPCLKA_CFGCR0_DDI_CLK_SEL (Results 1 – 2 of 2) sorted by relevance
4188 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DD… macro
1639 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in dg1_ddi_enable_clock()