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Searched refs:FMT_BIT_DEPTH_CONTROL (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.h45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
87 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
101 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
103 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
119 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
120 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
121 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
226 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
227 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
228 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
[all …]
H A Ddce_opp.c109 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
118 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
134 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
156 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
177 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
204 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
209 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
214 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
274 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
341 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/opp/dcn10/
H A Ddcn10_opp.c54 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in opp1_set_truncation()
65 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
122 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
H A Ddcn10_opp.h37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
54 uint32_t FMT_BIT_DEPTH_CONTROL; \
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v10_0.c539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v10_0_program_fmt()
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v10_0_program_fmt()
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
[all …]
H A Ddce_v11_0.c571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v11_0_program_fmt()
583 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
584 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
587 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
588 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v11_0_program_fmt()
596 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
597 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
600 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
[all …]
H A Dsid.h2104 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 macro
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h987 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
H A Devergreend.h1376 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
H A Dr600d.h1245 #define FMT_BIT_DEPTH_CONTROL 0x6710 macro
H A Dr600.c346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
H A Devergreen.c1345 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
H A Dcik.c8784 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h537 SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \