xref: /linux/drivers/usb/dwc2/hw.h (revision b258e426)
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3  * hw.h - DesignWare HS OTG Controller hardware definitions
4  *
5  * Copyright 2004-2013 Synopsys, Inc.
6  */
7 
8 #ifndef __DWC2_HW_H__
9 #define __DWC2_HW_H__
10 
11 #define HSOTG_REG(x)	(x)
12 
13 #define GOTGCTL				HSOTG_REG(0x000)
14 #define GOTGCTL_EUSB2_DISC_SUPP	BIT(28)
15 #define GOTGCTL_CHIRPEN			BIT(27)
16 #define GOTGCTL_MULT_VALID_BC_MASK	(0x1f << 22)
17 #define GOTGCTL_MULT_VALID_BC_SHIFT	22
18 #define GOTGCTL_CURMODE_HOST		BIT(21)
19 #define GOTGCTL_OTGVER			BIT(20)
20 #define GOTGCTL_BSESVLD			BIT(19)
21 #define GOTGCTL_ASESVLD			BIT(18)
22 #define GOTGCTL_DBNC_SHORT		BIT(17)
23 #define GOTGCTL_CONID_B			BIT(16)
24 #define GOTGCTL_DBNCE_FLTR_BYPASS	BIT(15)
25 #define GOTGCTL_DEVHNPEN		BIT(11)
26 #define GOTGCTL_HSTSETHNPEN		BIT(10)
27 #define GOTGCTL_HNPREQ			BIT(9)
28 #define GOTGCTL_HSTNEGSCS		BIT(8)
29 #define GOTGCTL_BVALOVAL		BIT(7)
30 #define GOTGCTL_BVALOEN			BIT(6)
31 #define GOTGCTL_AVALOVAL		BIT(5)
32 #define GOTGCTL_AVALOEN			BIT(4)
33 #define GOTGCTL_VBVALOVAL		BIT(3)
34 #define GOTGCTL_VBVALOEN		BIT(2)
35 #define GOTGCTL_SESREQ			BIT(1)
36 #define GOTGCTL_SESREQSCS		BIT(0)
37 
38 #define GOTGINT				HSOTG_REG(0x004)
39 #define GOTGINT_DBNCE_DONE		BIT(19)
40 #define GOTGINT_A_DEV_TOUT_CHG		BIT(18)
41 #define GOTGINT_HST_NEG_DET		BIT(17)
42 #define GOTGINT_HST_NEG_SUC_STS_CHNG	BIT(9)
43 #define GOTGINT_SES_REQ_SUC_STS_CHNG	BIT(8)
44 #define GOTGINT_SES_END_DET		BIT(2)
45 
46 #define GAHBCFG				HSOTG_REG(0x008)
47 #define GAHBCFG_AHB_SINGLE		BIT(23)
48 #define GAHBCFG_NOTI_ALL_DMA_WRIT	BIT(22)
49 #define GAHBCFG_REM_MEM_SUPP		BIT(21)
50 #define GAHBCFG_P_TXF_EMP_LVL		BIT(8)
51 #define GAHBCFG_NP_TXF_EMP_LVL		BIT(7)
52 #define GAHBCFG_DMA_EN			BIT(5)
53 #define GAHBCFG_HBSTLEN_MASK		(0xf << 1)
54 #define GAHBCFG_HBSTLEN_SHIFT		1
55 #define GAHBCFG_HBSTLEN_SINGLE		0
56 #define GAHBCFG_HBSTLEN_INCR		1
57 #define GAHBCFG_HBSTLEN_INCR4		3
58 #define GAHBCFG_HBSTLEN_INCR8		5
59 #define GAHBCFG_HBSTLEN_INCR16		7
60 #define GAHBCFG_GLBL_INTR_EN		BIT(0)
61 #define GAHBCFG_CTRL_MASK		(GAHBCFG_P_TXF_EMP_LVL | \
62 					 GAHBCFG_NP_TXF_EMP_LVL | \
63 					 GAHBCFG_DMA_EN | \
64 					 GAHBCFG_GLBL_INTR_EN)
65 
66 #define GUSBCFG				HSOTG_REG(0x00C)
67 #define GUSBCFG_FORCEDEVMODE		BIT(30)
68 #define GUSBCFG_FORCEHOSTMODE		BIT(29)
69 #define GUSBCFG_TXENDDELAY		BIT(28)
70 #define GUSBCFG_ICTRAFFICPULLREMOVE	BIT(27)
71 #define GUSBCFG_ICUSBCAP		BIT(26)
72 #define GUSBCFG_ULPI_INT_PROT_DIS	BIT(25)
73 #define GUSBCFG_INDICATORPASSTHROUGH	BIT(24)
74 #define GUSBCFG_INDICATORCOMPLEMENT	BIT(23)
75 #define GUSBCFG_TERMSELDLPULSE		BIT(22)
76 #define GUSBCFG_ULPI_INT_VBUS_IND	BIT(21)
77 #define GUSBCFG_ULPI_EXT_VBUS_DRV	BIT(20)
78 #define GUSBCFG_ULPI_CLK_SUSP_M		BIT(19)
79 #define GUSBCFG_ULPI_AUTO_RES		BIT(18)
80 #define GUSBCFG_ULPI_FS_LS		BIT(17)
81 #define GUSBCFG_OTG_UTMI_FS_SEL		BIT(16)
82 #define GUSBCFG_PHY_LP_CLK_SEL		BIT(15)
83 #define GUSBCFG_USBTRDTIM_MASK		(0xf << 10)
84 #define GUSBCFG_USBTRDTIM_SHIFT		10
85 #define GUSBCFG_HNPCAP			BIT(9)
86 #define GUSBCFG_SRPCAP			BIT(8)
87 #define GUSBCFG_DDRSEL			BIT(7)
88 #define GUSBCFG_PHYSEL			BIT(6)
89 #define GUSBCFG_FSINTF			BIT(5)
90 #define GUSBCFG_ULPI_UTMI_SEL		BIT(4)
91 #define GUSBCFG_PHYIF16			BIT(3)
92 #define GUSBCFG_PHYIF8			(0 << 3)
93 #define GUSBCFG_TOUTCAL_MASK		(0x7 << 0)
94 #define GUSBCFG_TOUTCAL_SHIFT		0
95 #define GUSBCFG_TOUTCAL_LIMIT		0x7
96 #define GUSBCFG_TOUTCAL(_x)		((_x) << 0)
97 
98 #define GRSTCTL				HSOTG_REG(0x010)
99 #define GRSTCTL_AHBIDLE			BIT(31)
100 #define GRSTCTL_DMAREQ			BIT(30)
101 #define GRSTCTL_CSFTRST_DONE		BIT(29)
102 #define GRSTCTL_CLOCK_SWITH_TIMER_MASK		(0x7 << 11)
103 #define GRSTCTL_CLOCK_SWITH_TIMER_SHIFT		11
104 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_19		0x0
105 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_15		0x1
106 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_147		0x2
107 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_50		0x3
108 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_100		0x4
109 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_125		0x5
110 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_200		0x6
111 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_DIS		0x7
112 #define GRSTCTL_CLOCK_SWITH_TIMER(_x)		((_x) << 11)
113 #define GRSTCTL_TXFNUM_MASK		(0x1f << 6)
114 #define GRSTCTL_TXFNUM_SHIFT		6
115 #define GRSTCTL_TXFNUM_LIMIT		0x1f
116 #define GRSTCTL_TXFNUM(_x)		((_x) << 6)
117 #define GRSTCTL_TXFFLSH			BIT(5)
118 #define GRSTCTL_RXFFLSH			BIT(4)
119 #define GRSTCTL_IN_TKNQ_FLSH		BIT(3)
120 #define GRSTCTL_FRMCNTRRST		BIT(2)
121 #define GRSTCTL_HSFTRST			BIT(1)
122 #define GRSTCTL_CSFTRST			BIT(0)
123 
124 #define GINTSTS				HSOTG_REG(0x014)
125 #define GINTMSK				HSOTG_REG(0x018)
126 #define GINTSTS_WKUPINT			BIT(31)
127 #define GINTSTS_SESSREQINT		BIT(30)
128 #define GINTSTS_DISCONNINT		BIT(29)
129 #define GINTSTS_CONIDSTSCHNG		BIT(28)
130 #define GINTSTS_LPMTRANRCVD		BIT(27)
131 #define GINTSTS_PTXFEMP			BIT(26)
132 #define GINTSTS_HCHINT			BIT(25)
133 #define GINTSTS_PRTINT			BIT(24)
134 #define GINTSTS_RESETDET		BIT(23)
135 #define GINTSTS_FET_SUSP		BIT(22)
136 #define GINTSTS_INCOMPL_IP		BIT(21)
137 #define GINTSTS_INCOMPL_SOOUT		BIT(21)
138 #define GINTSTS_INCOMPL_SOIN		BIT(20)
139 #define GINTSTS_OEPINT			BIT(19)
140 #define GINTSTS_IEPINT			BIT(18)
141 #define GINTSTS_EPMIS			BIT(17)
142 #define GINTSTS_RESTOREDONE		BIT(16)
143 #define GINTSTS_EOPF			BIT(15)
144 #define GINTSTS_ISOUTDROP		BIT(14)
145 #define GINTSTS_ENUMDONE		BIT(13)
146 #define GINTSTS_USBRST			BIT(12)
147 #define GINTSTS_USBSUSP			BIT(11)
148 #define GINTSTS_ERLYSUSP		BIT(10)
149 #define GINTSTS_I2CINT			BIT(9)
150 #define GINTSTS_ULPI_CK_INT		BIT(8)
151 #define GINTSTS_GOUTNAKEFF		BIT(7)
152 #define GINTSTS_GINNAKEFF		BIT(6)
153 #define GINTSTS_NPTXFEMP		BIT(5)
154 #define GINTSTS_RXFLVL			BIT(4)
155 #define GINTSTS_SOF			BIT(3)
156 #define GINTSTS_OTGINT			BIT(2)
157 #define GINTSTS_MODEMIS			BIT(1)
158 #define GINTSTS_CURMODE_HOST		BIT(0)
159 
160 #define GRXSTSR				HSOTG_REG(0x01C)
161 #define GRXSTSP				HSOTG_REG(0x020)
162 #define GRXSTS_FN_MASK			(0x7f << 25)
163 #define GRXSTS_FN_SHIFT			25
164 #define GRXSTS_PKTSTS_MASK		(0xf << 17)
165 #define GRXSTS_PKTSTS_SHIFT		17
166 #define GRXSTS_PKTSTS_GLOBALOUTNAK	1
167 #define GRXSTS_PKTSTS_OUTRX		2
168 #define GRXSTS_PKTSTS_HCHIN		2
169 #define GRXSTS_PKTSTS_OUTDONE		3
170 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP	3
171 #define GRXSTS_PKTSTS_SETUPDONE		4
172 #define GRXSTS_PKTSTS_DATATOGGLEERR	5
173 #define GRXSTS_PKTSTS_SETUPRX		6
174 #define GRXSTS_PKTSTS_HCHHALTED		7
175 #define GRXSTS_HCHNUM_MASK		(0xf << 0)
176 #define GRXSTS_HCHNUM_SHIFT		0
177 #define GRXSTS_DPID_MASK		(0x3 << 15)
178 #define GRXSTS_DPID_SHIFT		15
179 #define GRXSTS_BYTECNT_MASK		(0x7ff << 4)
180 #define GRXSTS_BYTECNT_SHIFT		4
181 #define GRXSTS_EPNUM_MASK		(0xf << 0)
182 #define GRXSTS_EPNUM_SHIFT		0
183 
184 #define GRXFSIZ				HSOTG_REG(0x024)
185 #define GRXFSIZ_DEPTH_MASK		(0xffff << 0)
186 #define GRXFSIZ_DEPTH_SHIFT		0
187 
188 #define GNPTXFSIZ			HSOTG_REG(0x028)
189 /* Use FIFOSIZE_* constants to access this register */
190 
191 #define GNPTXSTS			HSOTG_REG(0x02C)
192 #define GNPTXSTS_NP_TXQ_TOP_MASK		(0x7f << 24)
193 #define GNPTXSTS_NP_TXQ_TOP_SHIFT		24
194 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK		(0xff << 16)
195 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT		16
196 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)	(((_v) >> 16) & 0xff)
197 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK		(0xffff << 0)
198 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT		0
199 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)	(((_v) >> 0) & 0xffff)
200 
201 #define GI2CCTL				HSOTG_REG(0x0030)
202 #define GI2CCTL_BSYDNE			BIT(31)
203 #define GI2CCTL_RW			BIT(30)
204 #define GI2CCTL_I2CDATSE0		BIT(28)
205 #define GI2CCTL_I2CDEVADDR_MASK		(0x3 << 26)
206 #define GI2CCTL_I2CDEVADDR_SHIFT	26
207 #define GI2CCTL_I2CSUSPCTL		BIT(25)
208 #define GI2CCTL_ACK			BIT(24)
209 #define GI2CCTL_I2CEN			BIT(23)
210 #define GI2CCTL_ADDR_MASK		(0x7f << 16)
211 #define GI2CCTL_ADDR_SHIFT		16
212 #define GI2CCTL_REGADDR_MASK		(0xff << 8)
213 #define GI2CCTL_REGADDR_SHIFT		8
214 #define GI2CCTL_RWDATA_MASK		(0xff << 0)
215 #define GI2CCTL_RWDATA_SHIFT		0
216 
217 #define GPVNDCTL			HSOTG_REG(0x0034)
218 #define GGPIO				HSOTG_REG(0x0038)
219 #define GGPIO_STM32_OTG_GCCFG_PWRDWN	BIT(16)
220 #define GGPIO_STM32_OTG_GCCFG_VBDEN	BIT(21)
221 #define GGPIO_STM32_OTG_GCCFG_IDEN	BIT(22)
222 
223 #define GUID				HSOTG_REG(0x003c)
224 #define GSNPSID				HSOTG_REG(0x0040)
225 #define GHWCFG1				HSOTG_REG(0x0044)
226 #define GSNPSID_ID_MASK			GENMASK(31, 16)
227 
228 #define GHWCFG2				HSOTG_REG(0x0048)
229 #define GHWCFG2_OTG_ENABLE_IC_USB		BIT(31)
230 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1f << 26)
231 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT		26
232 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK	(0x3 << 24)
233 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT	24
234 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK	(0x3 << 22)
235 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT	22
236 #define GHWCFG2_MULTI_PROC_INT			BIT(20)
237 #define GHWCFG2_DYNAMIC_FIFO			BIT(19)
238 #define GHWCFG2_PERIO_EP_SUPPORTED		BIT(18)
239 #define GHWCFG2_NUM_HOST_CHAN_MASK		(0xf << 14)
240 #define GHWCFG2_NUM_HOST_CHAN_SHIFT		14
241 #define GHWCFG2_NUM_DEV_EP_MASK			(0xf << 10)
242 #define GHWCFG2_NUM_DEV_EP_SHIFT		10
243 #define GHWCFG2_FS_PHY_TYPE_MASK		(0x3 << 8)
244 #define GHWCFG2_FS_PHY_TYPE_SHIFT		8
245 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED	0
246 #define GHWCFG2_FS_PHY_TYPE_DEDICATED		1
247 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI		2
248 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI		3
249 #define GHWCFG2_HS_PHY_TYPE_MASK		(0x3 << 6)
250 #define GHWCFG2_HS_PHY_TYPE_SHIFT		6
251 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED	0
252 #define GHWCFG2_HS_PHY_TYPE_UTMI		1
253 #define GHWCFG2_HS_PHY_TYPE_ULPI		2
254 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI		3
255 #define GHWCFG2_POINT2POINT			BIT(5)
256 #define GHWCFG2_ARCHITECTURE_MASK		(0x3 << 3)
257 #define GHWCFG2_ARCHITECTURE_SHIFT		3
258 #define GHWCFG2_SLAVE_ONLY_ARCH			0
259 #define GHWCFG2_EXT_DMA_ARCH			1
260 #define GHWCFG2_INT_DMA_ARCH			2
261 #define GHWCFG2_OP_MODE_MASK			(0x7 << 0)
262 #define GHWCFG2_OP_MODE_SHIFT			0
263 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE		0
264 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE	1
265 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE	2
266 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE	3
267 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE	4
268 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST	5
269 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST	6
270 #define GHWCFG2_OP_MODE_UNDEFINED		7
271 
272 #define GHWCFG3				HSOTG_REG(0x004c)
273 #define GHWCFG3_DFIFO_DEPTH_MASK		(0xffff << 16)
274 #define GHWCFG3_DFIFO_DEPTH_SHIFT		16
275 #define GHWCFG3_OTG_LPM_EN			BIT(15)
276 #define GHWCFG3_BC_SUPPORT			BIT(14)
277 #define GHWCFG3_OTG_ENABLE_HSIC			BIT(13)
278 #define GHWCFG3_ADP_SUPP			BIT(12)
279 #define GHWCFG3_SYNCH_RESET_TYPE		BIT(11)
280 #define GHWCFG3_OPTIONAL_FEATURES		BIT(10)
281 #define GHWCFG3_VENDOR_CTRL_IF			BIT(9)
282 #define GHWCFG3_I2C				BIT(8)
283 #define GHWCFG3_OTG_FUNC			BIT(7)
284 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK	(0x7 << 4)
285 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT	4
286 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK	(0xf << 0)
287 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT	0
288 
289 #define GHWCFG4				HSOTG_REG(0x0050)
290 #define GHWCFG4_DESC_DMA_DYN			BIT(31)
291 #define GHWCFG4_DESC_DMA			BIT(30)
292 #define GHWCFG4_NUM_IN_EPS_MASK			(0xf << 26)
293 #define GHWCFG4_NUM_IN_EPS_SHIFT		26
294 #define GHWCFG4_DED_FIFO_EN			BIT(25)
295 #define GHWCFG4_DED_FIFO_SHIFT		25
296 #define GHWCFG4_SESSION_END_FILT_EN		BIT(24)
297 #define GHWCFG4_B_VALID_FILT_EN			BIT(23)
298 #define GHWCFG4_A_VALID_FILT_EN			BIT(22)
299 #define GHWCFG4_VBUS_VALID_FILT_EN		BIT(21)
300 #define GHWCFG4_IDDIG_FILT_EN			BIT(20)
301 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK	(0xf << 16)
302 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT	16
303 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK	(0x3 << 14)
304 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT	14
305 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8		0
306 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16		1
307 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16	2
308 #define GHWCFG4_ACG_SUPPORTED			BIT(12)
309 #define GHWCFG4_IPG_ISOC_SUPPORTED		BIT(11)
310 #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED      BIT(10)
311 #define GHWCFG4_XHIBER				BIT(7)
312 #define GHWCFG4_HIBER				BIT(6)
313 #define GHWCFG4_MIN_AHB_FREQ			BIT(5)
314 #define GHWCFG4_POWER_OPTIMIZ			BIT(4)
315 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK	(0xf << 0)
316 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT	0
317 
318 #define GLPMCFG				HSOTG_REG(0x0054)
319 #define GLPMCFG_INVSELHSIC		BIT(31)
320 #define GLPMCFG_HSICCON			BIT(30)
321 #define GLPMCFG_RSTRSLPSTS		BIT(29)
322 #define GLPMCFG_ENBESL			BIT(28)
323 #define GLPMCFG_LPM_RETRYCNT_STS_MASK	(0x7 << 25)
324 #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT	25
325 #define GLPMCFG_SNDLPM			BIT(24)
326 #define GLPMCFG_RETRY_CNT_MASK		(0x7 << 21)
327 #define GLPMCFG_RETRY_CNT_SHIFT		21
328 #define GLPMCFG_LPM_REJECT_CTRL_CONTROL	BIT(21)
329 #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC	BIT(22)
330 #define GLPMCFG_LPM_CHNL_INDX_MASK	(0xf << 17)
331 #define GLPMCFG_LPM_CHNL_INDX_SHIFT	17
332 #define GLPMCFG_L1RESUMEOK		BIT(16)
333 #define GLPMCFG_SLPSTS			BIT(15)
334 #define GLPMCFG_COREL1RES_MASK		(0x3 << 13)
335 #define GLPMCFG_COREL1RES_SHIFT		13
336 #define GLPMCFG_HIRD_THRES_MASK		(0x1f << 8)
337 #define GLPMCFG_HIRD_THRES_SHIFT	8
338 #define GLPMCFG_HIRD_THRES_EN		(0x10 << 8)
339 #define GLPMCFG_ENBLSLPM		BIT(7)
340 #define GLPMCFG_BREMOTEWAKE		BIT(6)
341 #define GLPMCFG_HIRD_MASK		(0xf << 2)
342 #define GLPMCFG_HIRD_SHIFT		2
343 #define GLPMCFG_APPL1RES		BIT(1)
344 #define GLPMCFG_LPMCAP			BIT(0)
345 
346 #define GPWRDN				HSOTG_REG(0x0058)
347 
348 #define GPWRDN_ULPI_LATCH_EN_DURING_HIB_ENTRY	BIT(29)
349 #define GPWRDN_MULT_VAL_ID_BC_MASK	(0x1f << 24)
350 #define GPWRDN_MULT_VAL_ID_BC_SHIFT	24
351 #define GPWRDN_ADP_INT			BIT(23)
352 #define GPWRDN_BSESSVLD			BIT(22)
353 #define GPWRDN_IDSTS			BIT(21)
354 #define GPWRDN_LINESTATE_MASK		(0x3 << 19)
355 #define GPWRDN_LINESTATE_SHIFT		19
356 #define GPWRDN_STS_CHGINT_MSK		BIT(18)
357 #define GPWRDN_STS_CHGINT		BIT(17)
358 #define GPWRDN_SRP_DET_MSK		BIT(16)
359 #define GPWRDN_SRP_DET			BIT(15)
360 #define GPWRDN_CONNECT_DET_MSK		BIT(14)
361 #define GPWRDN_CONNECT_DET		BIT(13)
362 #define GPWRDN_DISCONN_DET_MSK		BIT(12)
363 #define GPWRDN_DISCONN_DET		BIT(11)
364 #define GPWRDN_RST_DET_MSK		BIT(10)
365 #define GPWRDN_RST_DET			BIT(9)
366 #define GPWRDN_LNSTSCHG_MSK		BIT(8)
367 #define GPWRDN_LNSTSCHG			BIT(7)
368 #define GPWRDN_DIS_VBUS			BIT(6)
369 #define GPWRDN_PWRDNSWTCH		BIT(5)
370 #define GPWRDN_PWRDNRSTN		BIT(4)
371 #define GPWRDN_PWRDNCLMP		BIT(3)
372 #define GPWRDN_RESTORE			BIT(2)
373 #define GPWRDN_PMUACTV			BIT(1)
374 #define GPWRDN_PMUINTSEL		BIT(0)
375 
376 #define GDFIFOCFG			HSOTG_REG(0x005c)
377 #define GDFIFOCFG_EPINFOBASE_MASK	(0xffff << 16)
378 #define GDFIFOCFG_EPINFOBASE_SHIFT	16
379 #define GDFIFOCFG_GDFIFOCFG_MASK	(0xffff << 0)
380 #define GDFIFOCFG_GDFIFOCFG_SHIFT	0
381 
382 #define ADPCTL				HSOTG_REG(0x0060)
383 #define ADPCTL_AR_MASK			(0x3 << 27)
384 #define ADPCTL_AR_SHIFT			27
385 #define ADPCTL_ADP_TMOUT_INT_MSK	BIT(26)
386 #define ADPCTL_ADP_SNS_INT_MSK		BIT(25)
387 #define ADPCTL_ADP_PRB_INT_MSK		BIT(24)
388 #define ADPCTL_ADP_TMOUT_INT		BIT(23)
389 #define ADPCTL_ADP_SNS_INT		BIT(22)
390 #define ADPCTL_ADP_PRB_INT		BIT(21)
391 #define ADPCTL_ADPENA			BIT(20)
392 #define ADPCTL_ADPRES			BIT(19)
393 #define ADPCTL_ENASNS			BIT(18)
394 #define ADPCTL_ENAPRB			BIT(17)
395 #define ADPCTL_RTIM_MASK		(0x7ff << 6)
396 #define ADPCTL_RTIM_SHIFT		6
397 #define ADPCTL_PRB_PER_MASK		(0x3 << 4)
398 #define ADPCTL_PRB_PER_SHIFT		4
399 #define ADPCTL_PRB_DELTA_MASK		(0x3 << 2)
400 #define ADPCTL_PRB_DELTA_SHIFT		2
401 #define ADPCTL_PRB_DSCHRG_MASK		(0x3 << 0)
402 #define ADPCTL_PRB_DSCHRG_SHIFT		0
403 
404 #define GREFCLK				    HSOTG_REG(0x0064)
405 #define GREFCLK_REFCLKPER_MASK		    (0x1ffff << 15)
406 #define GREFCLK_REFCLKPER_SHIFT		    15
407 #define GREFCLK_REF_CLK_MODE		    BIT(14)
408 #define GREFCLK_SOF_CNT_WKUP_ALERT_MASK	    (0x3ff)
409 #define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT    0
410 
411 #define GINTMSK2			HSOTG_REG(0x0068)
412 #define GINTMSK2_WKUP_ALERT_INT_MSK	BIT(0)
413 
414 #define GINTSTS2			HSOTG_REG(0x006c)
415 #define GINTSTS2_WKUP_ALERT_INT		BIT(0)
416 
417 #define HPTXFSIZ			HSOTG_REG(0x100)
418 /* Use FIFOSIZE_* constants to access this register */
419 
420 #define DPTXFSIZN(_a)			HSOTG_REG(0x104 + (((_a) - 1) * 4))
421 /* Use FIFOSIZE_* constants to access this register */
422 
423 /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
424 #define FIFOSIZE_DEPTH_MASK		(0xffff << 16)
425 #define FIFOSIZE_DEPTH_SHIFT		16
426 #define FIFOSIZE_STARTADDR_MASK		(0xffff << 0)
427 #define FIFOSIZE_STARTADDR_SHIFT	0
428 #define FIFOSIZE_DEPTH_GET(_x)		(((_x) >> 16) & 0xffff)
429 
430 /* Device mode registers */
431 
432 #define DCFG				HSOTG_REG(0x800)
433 #define DCFG_DESCDMA_EN			BIT(23)
434 #define DCFG_EPMISCNT_MASK		(0x1f << 18)
435 #define DCFG_EPMISCNT_SHIFT		18
436 #define DCFG_EPMISCNT_LIMIT		0x1f
437 #define DCFG_EPMISCNT(_x)		((_x) << 18)
438 #define DCFG_IPG_ISOC_SUPPORDED		BIT(17)
439 #define DCFG_PERFRINT_MASK		(0x3 << 11)
440 #define DCFG_PERFRINT_SHIFT		11
441 #define DCFG_PERFRINT_LIMIT		0x3
442 #define DCFG_PERFRINT(_x)		((_x) << 11)
443 #define DCFG_DEVADDR_MASK		(0x7f << 4)
444 #define DCFG_DEVADDR_SHIFT		4
445 #define DCFG_DEVADDR_LIMIT		0x7f
446 #define DCFG_DEVADDR(_x)		((_x) << 4)
447 #define DCFG_NZ_STS_OUT_HSHK		BIT(2)
448 #define DCFG_DEVSPD_MASK		(0x3 << 0)
449 #define DCFG_DEVSPD_SHIFT		0
450 #define DCFG_DEVSPD_HS			0
451 #define DCFG_DEVSPD_FS			1
452 #define DCFG_DEVSPD_LS			2
453 #define DCFG_DEVSPD_FS48		3
454 
455 #define DCTL				HSOTG_REG(0x804)
456 #define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
457 #define DCTL_PWRONPRGDONE		BIT(11)
458 #define DCTL_CGOUTNAK			BIT(10)
459 #define DCTL_SGOUTNAK			BIT(9)
460 #define DCTL_CGNPINNAK			BIT(8)
461 #define DCTL_SGNPINNAK			BIT(7)
462 #define DCTL_TSTCTL_MASK		(0x7 << 4)
463 #define DCTL_TSTCTL_SHIFT		4
464 #define DCTL_GOUTNAKSTS			BIT(3)
465 #define DCTL_GNPINNAKSTS		BIT(2)
466 #define DCTL_SFTDISCON			BIT(1)
467 #define DCTL_RMTWKUPSIG			BIT(0)
468 
469 #define DSTS				HSOTG_REG(0x808)
470 #define DSTS_SOFFN_MASK			(0x3fff << 8)
471 #define DSTS_SOFFN_SHIFT		8
472 #define DSTS_SOFFN_LIMIT		0x3fff
473 #define DSTS_SOFFN(_x)			((_x) << 8)
474 #define DSTS_ERRATICERR			BIT(3)
475 #define DSTS_ENUMSPD_MASK		(0x3 << 1)
476 #define DSTS_ENUMSPD_SHIFT		1
477 #define DSTS_ENUMSPD_HS			0
478 #define DSTS_ENUMSPD_FS			1
479 #define DSTS_ENUMSPD_LS			2
480 #define DSTS_ENUMSPD_FS48		3
481 #define DSTS_SUSPSTS			BIT(0)
482 
483 #define DIEPMSK				HSOTG_REG(0x810)
484 #define DIEPMSK_NAKMSK			BIT(13)
485 #define DIEPMSK_BNAININTRMSK		BIT(9)
486 #define DIEPMSK_TXFIFOUNDRNMSK		BIT(8)
487 #define DIEPMSK_TXFIFOEMPTY		BIT(7)
488 #define DIEPMSK_INEPNAKEFFMSK		BIT(6)
489 #define DIEPMSK_INTKNEPMISMSK		BIT(5)
490 #define DIEPMSK_INTKNTXFEMPMSK		BIT(4)
491 #define DIEPMSK_TIMEOUTMSK		BIT(3)
492 #define DIEPMSK_AHBERRMSK		BIT(2)
493 #define DIEPMSK_EPDISBLDMSK		BIT(1)
494 #define DIEPMSK_XFERCOMPLMSK		BIT(0)
495 
496 #define DOEPMSK				HSOTG_REG(0x814)
497 #define DOEPMSK_BNAMSK			BIT(9)
498 #define DOEPMSK_BACK2BACKSETUP		BIT(6)
499 #define DOEPMSK_STSPHSERCVDMSK		BIT(5)
500 #define DOEPMSK_OUTTKNEPDISMSK		BIT(4)
501 #define DOEPMSK_SETUPMSK		BIT(3)
502 #define DOEPMSK_AHBERRMSK		BIT(2)
503 #define DOEPMSK_EPDISBLDMSK		BIT(1)
504 #define DOEPMSK_XFERCOMPLMSK		BIT(0)
505 
506 #define DAINT				HSOTG_REG(0x818)
507 #define DAINTMSK			HSOTG_REG(0x81C)
508 #define DAINT_OUTEP_SHIFT		16
509 #define DAINT_OUTEP(_x)			(1 << ((_x) + 16))
510 #define DAINT_INEP(_x)			(1 << (_x))
511 
512 #define DTKNQR1				HSOTG_REG(0x820)
513 #define DTKNQR2				HSOTG_REG(0x824)
514 #define DTKNQR3				HSOTG_REG(0x830)
515 #define DTKNQR4				HSOTG_REG(0x834)
516 #define DIEPEMPMSK			HSOTG_REG(0x834)
517 
518 #define DVBUSDIS			HSOTG_REG(0x828)
519 #define DVBUSPULSE			HSOTG_REG(0x82C)
520 
521 #define DIEPCTL0			HSOTG_REG(0x900)
522 #define DIEPCTL(_a)			HSOTG_REG(0x900 + ((_a) * 0x20))
523 
524 #define DOEPCTL0			HSOTG_REG(0xB00)
525 #define DOEPCTL(_a)			HSOTG_REG(0xB00 + ((_a) * 0x20))
526 
527 /* EP0 specialness:
528  * bits[29..28] - reserved (no SetD0PID, SetD1PID)
529  * bits[25..22] - should always be zero, this isn't a periodic endpoint
530  * bits[10..0]  - MPS setting different for EP0
531  */
532 #define D0EPCTL_MPS_MASK		(0x3 << 0)
533 #define D0EPCTL_MPS_SHIFT		0
534 #define D0EPCTL_MPS_64			0
535 #define D0EPCTL_MPS_32			1
536 #define D0EPCTL_MPS_16			2
537 #define D0EPCTL_MPS_8			3
538 
539 #define DXEPCTL_EPENA			BIT(31)
540 #define DXEPCTL_EPDIS			BIT(30)
541 #define DXEPCTL_SETD1PID		BIT(29)
542 #define DXEPCTL_SETODDFR		BIT(29)
543 #define DXEPCTL_SETD0PID		BIT(28)
544 #define DXEPCTL_SETEVENFR		BIT(28)
545 #define DXEPCTL_SNAK			BIT(27)
546 #define DXEPCTL_CNAK			BIT(26)
547 #define DXEPCTL_TXFNUM_MASK		(0xf << 22)
548 #define DXEPCTL_TXFNUM_SHIFT		22
549 #define DXEPCTL_TXFNUM_LIMIT		0xf
550 #define DXEPCTL_TXFNUM(_x)		((_x) << 22)
551 #define DXEPCTL_STALL			BIT(21)
552 #define DXEPCTL_SNP			BIT(20)
553 #define DXEPCTL_EPTYPE_MASK		(0x3 << 18)
554 #define DXEPCTL_EPTYPE_CONTROL		(0x0 << 18)
555 #define DXEPCTL_EPTYPE_ISO		(0x1 << 18)
556 #define DXEPCTL_EPTYPE_BULK		(0x2 << 18)
557 #define DXEPCTL_EPTYPE_INTERRUPT	(0x3 << 18)
558 
559 #define DXEPCTL_NAKSTS			BIT(17)
560 #define DXEPCTL_DPID			BIT(16)
561 #define DXEPCTL_EOFRNUM			BIT(16)
562 #define DXEPCTL_USBACTEP		BIT(15)
563 #define DXEPCTL_NEXTEP_MASK		(0xf << 11)
564 #define DXEPCTL_NEXTEP_SHIFT		11
565 #define DXEPCTL_NEXTEP_LIMIT		0xf
566 #define DXEPCTL_NEXTEP(_x)		((_x) << 11)
567 #define DXEPCTL_MPS_MASK		(0x7ff << 0)
568 #define DXEPCTL_MPS_SHIFT		0
569 #define DXEPCTL_MPS_LIMIT		0x7ff
570 #define DXEPCTL_MPS(_x)			((_x) << 0)
571 
572 #define DIEPINT(_a)			HSOTG_REG(0x908 + ((_a) * 0x20))
573 #define DOEPINT(_a)			HSOTG_REG(0xB08 + ((_a) * 0x20))
574 #define DXEPINT_SETUP_RCVD		BIT(15)
575 #define DXEPINT_NYETINTRPT		BIT(14)
576 #define DXEPINT_NAKINTRPT		BIT(13)
577 #define DXEPINT_BBLEERRINTRPT		BIT(12)
578 #define DXEPINT_PKTDRPSTS		BIT(11)
579 #define DXEPINT_BNAINTR			BIT(9)
580 #define DXEPINT_TXFIFOUNDRN		BIT(8)
581 #define DXEPINT_OUTPKTERR		BIT(8)
582 #define DXEPINT_TXFEMP			BIT(7)
583 #define DXEPINT_INEPNAKEFF		BIT(6)
584 #define DXEPINT_BACK2BACKSETUP		BIT(6)
585 #define DXEPINT_INTKNEPMIS		BIT(5)
586 #define DXEPINT_STSPHSERCVD		BIT(5)
587 #define DXEPINT_INTKNTXFEMP		BIT(4)
588 #define DXEPINT_OUTTKNEPDIS		BIT(4)
589 #define DXEPINT_TIMEOUT			BIT(3)
590 #define DXEPINT_SETUP			BIT(3)
591 #define DXEPINT_AHBERR			BIT(2)
592 #define DXEPINT_EPDISBLD		BIT(1)
593 #define DXEPINT_XFERCOMPL		BIT(0)
594 
595 #define DIEPTSIZ0			HSOTG_REG(0x910)
596 #define DIEPTSIZ0_PKTCNT_MASK		(0x3 << 19)
597 #define DIEPTSIZ0_PKTCNT_SHIFT		19
598 #define DIEPTSIZ0_PKTCNT_LIMIT		0x3
599 #define DIEPTSIZ0_PKTCNT(_x)		((_x) << 19)
600 #define DIEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
601 #define DIEPTSIZ0_XFERSIZE_SHIFT	0
602 #define DIEPTSIZ0_XFERSIZE_LIMIT	0x7f
603 #define DIEPTSIZ0_XFERSIZE(_x)		((_x) << 0)
604 
605 #define DOEPTSIZ0			HSOTG_REG(0xB10)
606 #define DOEPTSIZ0_SUPCNT_MASK		(0x3 << 29)
607 #define DOEPTSIZ0_SUPCNT_SHIFT		29
608 #define DOEPTSIZ0_SUPCNT_LIMIT		0x3
609 #define DOEPTSIZ0_SUPCNT(_x)		((_x) << 29)
610 #define DOEPTSIZ0_PKTCNT		BIT(19)
611 #define DOEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
612 #define DOEPTSIZ0_XFERSIZE_SHIFT	0
613 
614 #define DIEPTSIZ(_a)			HSOTG_REG(0x910 + ((_a) * 0x20))
615 #define DOEPTSIZ(_a)			HSOTG_REG(0xB10 + ((_a) * 0x20))
616 #define DXEPTSIZ_MC_MASK		(0x3 << 29)
617 #define DXEPTSIZ_MC_SHIFT		29
618 #define DXEPTSIZ_MC_LIMIT		0x3
619 #define DXEPTSIZ_MC(_x)			((_x) << 29)
620 #define DXEPTSIZ_PKTCNT_MASK		(0x3ff << 19)
621 #define DXEPTSIZ_PKTCNT_SHIFT		19
622 #define DXEPTSIZ_PKTCNT_LIMIT		0x3ff
623 #define DXEPTSIZ_PKTCNT_GET(_v)		(((_v) >> 19) & 0x3ff)
624 #define DXEPTSIZ_PKTCNT(_x)		((_x) << 19)
625 #define DXEPTSIZ_XFERSIZE_MASK		(0x7ffff << 0)
626 #define DXEPTSIZ_XFERSIZE_SHIFT		0
627 #define DXEPTSIZ_XFERSIZE_LIMIT		0x7ffff
628 #define DXEPTSIZ_XFERSIZE_GET(_v)	(((_v) >> 0) & 0x7ffff)
629 #define DXEPTSIZ_XFERSIZE(_x)		((_x) << 0)
630 
631 #define DIEPDMA(_a)			HSOTG_REG(0x914 + ((_a) * 0x20))
632 #define DOEPDMA(_a)			HSOTG_REG(0xB14 + ((_a) * 0x20))
633 
634 #define DTXFSTS(_a)			HSOTG_REG(0x918 + ((_a) * 0x20))
635 
636 #define PCGCTL				HSOTG_REG(0x0e00)
637 #define PCGCTL_IF_DEV_MODE		BIT(31)
638 #define PCGCTL_P2HD_PRT_SPD_MASK	(0x3 << 29)
639 #define PCGCTL_P2HD_PRT_SPD_SHIFT	29
640 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK	(0x3 << 27)
641 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT	27
642 #define PCGCTL_MAC_DEV_ADDR_MASK	(0x7f << 20)
643 #define PCGCTL_MAC_DEV_ADDR_SHIFT	20
644 #define PCGCTL_MAX_TERMSEL		BIT(19)
645 #define PCGCTL_MAX_XCVRSELECT_MASK	(0x3 << 17)
646 #define PCGCTL_MAX_XCVRSELECT_SHIFT	17
647 #define PCGCTL_PORT_POWER		BIT(16)
648 #define PCGCTL_PRT_CLK_SEL_MASK		(0x3 << 14)
649 #define PCGCTL_PRT_CLK_SEL_SHIFT	14
650 #define PCGCTL_ESS_REG_RESTORED		BIT(13)
651 #define PCGCTL_EXTND_HIBER_SWITCH	BIT(12)
652 #define PCGCTL_EXTND_HIBER_PWRCLMP	BIT(11)
653 #define PCGCTL_ENBL_EXTND_HIBER		BIT(10)
654 #define PCGCTL_RESTOREMODE		BIT(9)
655 #define PCGCTL_RESETAFTSUSP		BIT(8)
656 #define PCGCTL_DEEP_SLEEP		BIT(7)
657 #define PCGCTL_PHY_IN_SLEEP		BIT(6)
658 #define PCGCTL_ENBL_SLEEP_GATING	BIT(5)
659 #define PCGCTL_RSTPDWNMODULE		BIT(3)
660 #define PCGCTL_PWRCLMP			BIT(2)
661 #define PCGCTL_GATEHCLK			BIT(1)
662 #define PCGCTL_STOPPCLK			BIT(0)
663 
664 #define PCGCCTL1                        HSOTG_REG(0xe04)
665 #define PCGCCTL1_TIMER                  (0x3 << 1)
666 #define PCGCCTL1_GATEEN                 BIT(0)
667 
668 #define EPFIFO(_a)			HSOTG_REG(0x1000 + ((_a) * 0x1000))
669 
670 /* Host Mode Registers */
671 
672 #define HCFG				HSOTG_REG(0x0400)
673 #define HCFG_MODECHTIMEN		BIT(31)
674 #define HCFG_PERSCHEDENA		BIT(26)
675 #define HCFG_FRLISTEN_MASK		(0x3 << 24)
676 #define HCFG_FRLISTEN_SHIFT		24
677 #define HCFG_FRLISTEN_8				(0 << 24)
678 #define FRLISTEN_8_SIZE				8
679 #define HCFG_FRLISTEN_16			BIT(24)
680 #define FRLISTEN_16_SIZE			16
681 #define HCFG_FRLISTEN_32			(2 << 24)
682 #define FRLISTEN_32_SIZE			32
683 #define HCFG_FRLISTEN_64			(3 << 24)
684 #define FRLISTEN_64_SIZE			64
685 #define HCFG_DESCDMA			BIT(23)
686 #define HCFG_RESVALID_MASK		(0xff << 8)
687 #define HCFG_RESVALID_SHIFT		8
688 #define HCFG_ENA32KHZ			BIT(7)
689 #define HCFG_FSLSSUPP			BIT(2)
690 #define HCFG_FSLSPCLKSEL_MASK		(0x3 << 0)
691 #define HCFG_FSLSPCLKSEL_SHIFT		0
692 #define HCFG_FSLSPCLKSEL_30_60_MHZ	0
693 #define HCFG_FSLSPCLKSEL_48_MHZ		1
694 #define HCFG_FSLSPCLKSEL_6_MHZ		2
695 
696 #define HFIR				HSOTG_REG(0x0404)
697 #define HFIR_FRINT_MASK			(0xffff << 0)
698 #define HFIR_FRINT_SHIFT		0
699 #define HFIR_RLDCTRL			BIT(16)
700 
701 #define HFNUM				HSOTG_REG(0x0408)
702 #define HFNUM_FRREM_MASK		(0xffff << 16)
703 #define HFNUM_FRREM_SHIFT		16
704 #define HFNUM_FRNUM_MASK		(0xffff << 0)
705 #define HFNUM_FRNUM_SHIFT		0
706 #define HFNUM_MAX_FRNUM			0x3fff
707 
708 #define HPTXSTS				HSOTG_REG(0x0410)
709 #define TXSTS_QTOP_ODD			BIT(31)
710 #define TXSTS_QTOP_CHNEP_MASK		(0xf << 27)
711 #define TXSTS_QTOP_CHNEP_SHIFT		27
712 #define TXSTS_QTOP_TOKEN_MASK		(0x3 << 25)
713 #define TXSTS_QTOP_TOKEN_SHIFT		25
714 #define TXSTS_QTOP_TERMINATE		BIT(24)
715 #define TXSTS_QSPCAVAIL_MASK		(0x7f << 16)
716 #define TXSTS_QSPCAVAIL_SHIFT		16
717 #define TXSTS_FSPCAVAIL_MASK		(0xffff << 0)
718 #define TXSTS_FSPCAVAIL_SHIFT		0
719 
720 #define HAINT				HSOTG_REG(0x0414)
721 #define HAINTMSK			HSOTG_REG(0x0418)
722 #define HFLBADDR			HSOTG_REG(0x041c)
723 
724 #define HPRT0				HSOTG_REG(0x0440)
725 #define HPRT0_SPD_MASK			(0x3 << 17)
726 #define HPRT0_SPD_SHIFT			17
727 #define HPRT0_SPD_HIGH_SPEED		0
728 #define HPRT0_SPD_FULL_SPEED		1
729 #define HPRT0_SPD_LOW_SPEED		2
730 #define HPRT0_TSTCTL_MASK		(0xf << 13)
731 #define HPRT0_TSTCTL_SHIFT		13
732 #define HPRT0_PWR			BIT(12)
733 #define HPRT0_LNSTS_MASK		(0x3 << 10)
734 #define HPRT0_LNSTS_SHIFT		10
735 #define HPRT0_RST			BIT(8)
736 #define HPRT0_SUSP			BIT(7)
737 #define HPRT0_RES			BIT(6)
738 #define HPRT0_OVRCURRCHG		BIT(5)
739 #define HPRT0_OVRCURRACT		BIT(4)
740 #define HPRT0_ENACHG			BIT(3)
741 #define HPRT0_ENA			BIT(2)
742 #define HPRT0_CONNDET			BIT(1)
743 #define HPRT0_CONNSTS			BIT(0)
744 
745 #define HCCHAR(_ch)			HSOTG_REG(0x0500 + 0x20 * (_ch))
746 #define HCCHAR_CHENA			BIT(31)
747 #define HCCHAR_CHDIS			BIT(30)
748 #define HCCHAR_ODDFRM			BIT(29)
749 #define HCCHAR_DEVADDR_MASK		(0x7f << 22)
750 #define HCCHAR_DEVADDR_SHIFT		22
751 #define HCCHAR_MULTICNT_MASK		(0x3 << 20)
752 #define HCCHAR_MULTICNT_SHIFT		20
753 #define HCCHAR_EPTYPE_MASK		(0x3 << 18)
754 #define HCCHAR_EPTYPE_SHIFT		18
755 #define HCCHAR_LSPDDEV			BIT(17)
756 #define HCCHAR_EPDIR			BIT(15)
757 #define HCCHAR_EPNUM_MASK		(0xf << 11)
758 #define HCCHAR_EPNUM_SHIFT		11
759 #define HCCHAR_MPS_MASK			(0x7ff << 0)
760 #define HCCHAR_MPS_SHIFT		0
761 
762 #define HCSPLT(_ch)			HSOTG_REG(0x0504 + 0x20 * (_ch))
763 #define HCSPLT_SPLTENA			BIT(31)
764 #define HCSPLT_COMPSPLT			BIT(16)
765 #define HCSPLT_XACTPOS_MASK		(0x3 << 14)
766 #define HCSPLT_XACTPOS_SHIFT		14
767 #define HCSPLT_XACTPOS_MID		0
768 #define HCSPLT_XACTPOS_END		1
769 #define HCSPLT_XACTPOS_BEGIN		2
770 #define HCSPLT_XACTPOS_ALL		3
771 #define HCSPLT_HUBADDR_MASK		(0x7f << 7)
772 #define HCSPLT_HUBADDR_SHIFT		7
773 #define HCSPLT_PRTADDR_MASK		(0x7f << 0)
774 #define HCSPLT_PRTADDR_SHIFT		0
775 
776 #define HCINT(_ch)			HSOTG_REG(0x0508 + 0x20 * (_ch))
777 #define HCINTMSK(_ch)			HSOTG_REG(0x050c + 0x20 * (_ch))
778 #define HCINTMSK_RESERVED14_31		(0x3ffff << 14)
779 #define HCINTMSK_FRM_LIST_ROLL		BIT(13)
780 #define HCINTMSK_XCS_XACT		BIT(12)
781 #define HCINTMSK_BNA			BIT(11)
782 #define HCINTMSK_DATATGLERR		BIT(10)
783 #define HCINTMSK_FRMOVRUN		BIT(9)
784 #define HCINTMSK_BBLERR			BIT(8)
785 #define HCINTMSK_XACTERR		BIT(7)
786 #define HCINTMSK_NYET			BIT(6)
787 #define HCINTMSK_ACK			BIT(5)
788 #define HCINTMSK_NAK			BIT(4)
789 #define HCINTMSK_STALL			BIT(3)
790 #define HCINTMSK_AHBERR			BIT(2)
791 #define HCINTMSK_CHHLTD			BIT(1)
792 #define HCINTMSK_XFERCOMPL		BIT(0)
793 
794 #define HCTSIZ(_ch)			HSOTG_REG(0x0510 + 0x20 * (_ch))
795 #define TSIZ_DOPNG			BIT(31)
796 #define TSIZ_SC_MC_PID_MASK		(0x3 << 29)
797 #define TSIZ_SC_MC_PID_SHIFT		29
798 #define TSIZ_SC_MC_PID_DATA0		0
799 #define TSIZ_SC_MC_PID_DATA2		1
800 #define TSIZ_SC_MC_PID_DATA1		2
801 #define TSIZ_SC_MC_PID_MDATA		3
802 #define TSIZ_SC_MC_PID_SETUP		3
803 #define TSIZ_PKTCNT_MASK		(0x3ff << 19)
804 #define TSIZ_PKTCNT_SHIFT		19
805 #define TSIZ_NTD_MASK			(0xff << 8)
806 #define TSIZ_NTD_SHIFT			8
807 #define TSIZ_SCHINFO_MASK		(0xff << 0)
808 #define TSIZ_SCHINFO_SHIFT		0
809 #define TSIZ_XFERSIZE_MASK		(0x7ffff << 0)
810 #define TSIZ_XFERSIZE_SHIFT		0
811 
812 #define HCDMA(_ch)			HSOTG_REG(0x0514 + 0x20 * (_ch))
813 
814 #define HCDMAB(_ch)			HSOTG_REG(0x051c + 0x20 * (_ch))
815 
816 #define HCFIFO(_ch)			HSOTG_REG(0x1000 + 0x1000 * (_ch))
817 
818 /**
819  * struct dwc2_dma_desc - DMA descriptor structure,
820  * used for both host and gadget modes
821  *
822  * @status: DMA descriptor status quadlet
823  * @buf:    DMA descriptor data buffer pointer
824  *
825  * DMA Descriptor structure contains two quadlets:
826  * Status quadlet and Data buffer pointer.
827  */
828 struct dwc2_dma_desc {
829 	u32 status;
830 	u32 buf;
831 } __packed;
832 
833 /* Host Mode DMA descriptor status quadlet */
834 
835 #define HOST_DMA_A			BIT(31)
836 #define HOST_DMA_STS_MASK		(0x3 << 28)
837 #define HOST_DMA_STS_SHIFT		28
838 #define HOST_DMA_STS_PKTERR		BIT(28)
839 #define HOST_DMA_EOL			BIT(26)
840 #define HOST_DMA_IOC			BIT(25)
841 #define HOST_DMA_SUP			BIT(24)
842 #define HOST_DMA_ALT_QTD		BIT(23)
843 #define HOST_DMA_QTD_OFFSET_MASK	(0x3f << 17)
844 #define HOST_DMA_QTD_OFFSET_SHIFT	17
845 #define HOST_DMA_ISOC_NBYTES_MASK	(0xfff << 0)
846 #define HOST_DMA_ISOC_NBYTES_SHIFT	0
847 #define HOST_DMA_NBYTES_MASK		(0x1ffff << 0)
848 #define HOST_DMA_NBYTES_SHIFT		0
849 #define HOST_DMA_NBYTES_LIMIT		131071
850 
851 /* Device Mode DMA descriptor status quadlet */
852 
853 #define DEV_DMA_BUFF_STS_MASK		(0x3 << 30)
854 #define DEV_DMA_BUFF_STS_SHIFT		30
855 #define DEV_DMA_BUFF_STS_HREADY		0
856 #define DEV_DMA_BUFF_STS_DMABUSY	1
857 #define DEV_DMA_BUFF_STS_DMADONE	2
858 #define DEV_DMA_BUFF_STS_HBUSY		3
859 #define DEV_DMA_STS_MASK		(0x3 << 28)
860 #define DEV_DMA_STS_SHIFT		28
861 #define DEV_DMA_STS_SUCC		0
862 #define DEV_DMA_STS_BUFF_FLUSH		1
863 #define DEV_DMA_STS_BUFF_ERR		3
864 #define DEV_DMA_L			BIT(27)
865 #define DEV_DMA_SHORT			BIT(26)
866 #define DEV_DMA_IOC			BIT(25)
867 #define DEV_DMA_SR			BIT(24)
868 #define DEV_DMA_MTRF			BIT(23)
869 #define DEV_DMA_ISOC_PID_MASK		(0x3 << 23)
870 #define DEV_DMA_ISOC_PID_SHIFT		23
871 #define DEV_DMA_ISOC_PID_DATA0		0
872 #define DEV_DMA_ISOC_PID_DATA2		1
873 #define DEV_DMA_ISOC_PID_DATA1		2
874 #define DEV_DMA_ISOC_PID_MDATA		3
875 #define DEV_DMA_ISOC_FRNUM_MASK		(0x7ff << 12)
876 #define DEV_DMA_ISOC_FRNUM_SHIFT	12
877 #define DEV_DMA_ISOC_TX_NBYTES_MASK	(0xfff << 0)
878 #define DEV_DMA_ISOC_TX_NBYTES_LIMIT	0xfff
879 #define DEV_DMA_ISOC_RX_NBYTES_MASK	(0x7ff << 0)
880 #define DEV_DMA_ISOC_RX_NBYTES_LIMIT	0x7ff
881 #define DEV_DMA_ISOC_NBYTES_SHIFT	0
882 #define DEV_DMA_NBYTES_MASK		(0xffff << 0)
883 #define DEV_DMA_NBYTES_SHIFT		0
884 #define DEV_DMA_NBYTES_LIMIT		0xffff
885 
886 #define MAX_DMA_DESC_NUM_GENERIC	64
887 #define MAX_DMA_DESC_NUM_HS_ISOC	256
888 
889 #endif /* __DWC2_HW_H__ */
890