1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3 
4 #ifndef __HCLGEVF_CMD_H
5 #define __HCLGEVF_CMD_H
6 #include <linux/io.h>
7 #include <linux/types.h>
8 #include "hnae3.h"
9 #include "hclge_comm_cmd.h"
10 
11 #define HCLGEVF_CMDQ_RX_INVLD_B		0
12 #define HCLGEVF_CMDQ_RX_OUTVLD_B	1
13 
14 struct hclgevf_hw;
15 struct hclgevf_dev;
16 
17 #define HCLGEVF_SYNC_RX_RING_HEAD_EN_B	4
18 
19 #define HCLGEVF_TQP_REG_OFFSET		0x80000
20 #define HCLGEVF_TQP_REG_SIZE		0x200
21 
22 #define HCLGEVF_TQP_MAX_SIZE_DEV_V2	1024
23 #define HCLGEVF_TQP_EXT_REG_OFFSET	0x100
24 
25 struct hclgevf_tqp_map {
26 	__le16 tqp_id;	/* Absolute tqp id for in this pf */
27 	u8 tqp_vf; /* VF id */
28 #define HCLGEVF_TQP_MAP_TYPE_PF		0
29 #define HCLGEVF_TQP_MAP_TYPE_VF		1
30 #define HCLGEVF_TQP_MAP_TYPE_B		0
31 #define HCLGEVF_TQP_MAP_EN_B		1
32 	u8 tqp_flag;	/* Indicate it's pf or vf tqp */
33 	__le16 tqp_vid; /* Virtual id in this pf/vf */
34 	u8 rsv[18];
35 };
36 
37 #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD	10
38 
39 enum hclgevf_int_type {
40 	HCLGEVF_INT_TX = 0,
41 	HCLGEVF_INT_RX,
42 	HCLGEVF_INT_EVENT,
43 };
44 
45 struct hclgevf_ctrl_vector_chain {
46 	u8 int_vector_id;
47 	u8 int_cause_num;
48 #define HCLGEVF_INT_TYPE_S	0
49 #define HCLGEVF_INT_TYPE_M	0x3
50 #define HCLGEVF_TQP_ID_S	2
51 #define HCLGEVF_TQP_ID_M	(0x3fff << HCLGEVF_TQP_ID_S)
52 	__le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD];
53 	u8 vfid;
54 	u8 resv;
55 };
56 
57 #define HCLGEVF_MSIX_OFT_ROCEE_S       0
58 #define HCLGEVF_MSIX_OFT_ROCEE_M       (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
59 #define HCLGEVF_VEC_NUM_S              0
60 #define HCLGEVF_VEC_NUM_M              (0xff << HCLGEVF_VEC_NUM_S)
61 struct hclgevf_query_res_cmd {
62 	__le16 tqp_num;
63 	__le16 reserved;
64 	__le16 msixcap_localid_ba_nic;
65 	__le16 msixcap_localid_ba_rocee;
66 	__le16 vf_intr_vector_number;
67 	__le16 rsv[7];
68 };
69 
70 #define HCLGEVF_GRO_EN_B               0
71 struct hclgevf_cfg_gro_status_cmd {
72 	u8 gro_en;
73 	u8 rsv[23];
74 };
75 
76 #define HCLGEVF_LINK_STS_B	0
77 #define HCLGEVF_LINK_STATUS	BIT(HCLGEVF_LINK_STS_B)
78 struct hclgevf_link_status_cmd {
79 	u8 status;
80 	u8 rsv[23];
81 };
82 
83 #define HCLGEVF_RING_ID_MASK	0x3ff
84 #define HCLGEVF_TQP_ENABLE_B	0
85 
86 struct hclgevf_cfg_com_tqp_queue_cmd {
87 	__le16 tqp_id;
88 	__le16 stream_id;
89 	u8 enable;
90 	u8 rsv[19];
91 };
92 
93 struct hclgevf_cfg_tx_queue_pointer_cmd {
94 	__le16 tqp_id;
95 	__le16 tx_tail;
96 	__le16 tx_head;
97 	__le16 fbd_num;
98 	__le16 ring_offset;
99 	u8 rsv[14];
100 };
101 
102 /* this bit indicates that the driver is ready for hardware reset */
103 #define HCLGEVF_NIC_SW_RST_RDY_B	16
104 #define HCLGEVF_NIC_SW_RST_RDY		BIT(HCLGEVF_NIC_SW_RST_RDY_B)
105 
106 #define HCLGEVF_NIC_CMQ_DESC_NUM	1024
107 #define HCLGEVF_NIC_CMQ_DESC_NUM_S	3
108 
109 #define HCLGEVF_QUERY_DEV_SPECS_BD_NUM		4
110 
111 #define hclgevf_cmd_setup_basic_desc(desc, opcode, is_read) \
112 	hclge_comm_cmd_setup_basic_desc(desc, opcode, is_read)
113 
114 struct hclgevf_dev_specs_0_cmd {
115 	__le32 rsv0;
116 	__le32 mac_entry_num;
117 	__le32 mng_entry_num;
118 	__le16 rss_ind_tbl_size;
119 	__le16 rss_key_size;
120 	__le16 int_ql_max;
121 	u8 max_non_tso_bd_num;
122 	u8 rsv1[5];
123 };
124 
125 #define HCLGEVF_DEF_MAX_INT_GL		0x1FE0U
126 
127 struct hclgevf_dev_specs_1_cmd {
128 	__le16 max_frm_size;
129 	__le16 rsv0;
130 	__le16 max_int_gl;
131 	u8 rsv1[18];
132 };
133 
134 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num);
135 void hclgevf_arq_init(struct hclgevf_dev *hdev);
136 #endif
137