1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3 
4 #ifndef _IAVF_TYPE_H_
5 #define _IAVF_TYPE_H_
6 
7 #include "iavf_status.h"
8 #include "iavf_osdep.h"
9 #include "iavf_register.h"
10 #include "iavf_adminq.h"
11 #include "iavf_devids.h"
12 
13 /* IAVF_MASK is a macro used on 32 bit registers */
14 #define IAVF_MASK(mask, shift) ((u32)(mask) << (shift))
15 
16 #define IAVF_MAX_VSI_QP			16
17 #define IAVF_MAX_VF_VSI			3
18 #define IAVF_MAX_CHAINED_RX_BUFFERS	5
19 
20 /* forward declaration */
21 struct iavf_hw;
22 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);
23 
24 /* Data type manipulation macros. */
25 
26 #define IAVF_DESC_UNUSED(R)	\
27 	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
28 	(R)->next_to_clean - (R)->next_to_use - 1)
29 
30 /* bitfields for Tx queue mapping in QTX_CTL */
31 #define IAVF_QTX_CTL_VF_QUEUE	0x0
32 #define IAVF_QTX_CTL_VM_QUEUE	0x1
33 #define IAVF_QTX_CTL_PF_QUEUE	0x2
34 
35 /* debug masks - set these bits in hw->debug_mask to control output */
36 enum iavf_debug_mask {
37 	IAVF_DEBUG_INIT			= 0x00000001,
38 	IAVF_DEBUG_RELEASE		= 0x00000002,
39 
40 	IAVF_DEBUG_LINK			= 0x00000010,
41 	IAVF_DEBUG_PHY			= 0x00000020,
42 	IAVF_DEBUG_HMC			= 0x00000040,
43 	IAVF_DEBUG_NVM			= 0x00000080,
44 	IAVF_DEBUG_LAN			= 0x00000100,
45 	IAVF_DEBUG_FLOW			= 0x00000200,
46 	IAVF_DEBUG_DCB			= 0x00000400,
47 	IAVF_DEBUG_DIAG			= 0x00000800,
48 	IAVF_DEBUG_FD			= 0x00001000,
49 	IAVF_DEBUG_PACKAGE		= 0x00002000,
50 
51 	IAVF_DEBUG_AQ_MESSAGE		= 0x01000000,
52 	IAVF_DEBUG_AQ_DESCRIPTOR	= 0x02000000,
53 	IAVF_DEBUG_AQ_DESC_BUFFER	= 0x04000000,
54 	IAVF_DEBUG_AQ_COMMAND		= 0x06000000,
55 	IAVF_DEBUG_AQ			= 0x0F000000,
56 
57 	IAVF_DEBUG_USER			= 0xF0000000,
58 
59 	IAVF_DEBUG_ALL			= 0xFFFFFFFF
60 };
61 
62 /* These are structs for managing the hardware information and the operations.
63  * The structures of function pointers are filled out at init time when we
64  * know for sure exactly which hardware we're working with.  This gives us the
65  * flexibility of using the same main driver code but adapting to slightly
66  * different hardware needs as new parts are developed.  For this architecture,
67  * the Firmware and AdminQ are intended to insulate the driver from most of the
68  * future changes, but these structures will also do part of the job.
69  */
70 enum iavf_vsi_type {
71 	IAVF_VSI_MAIN	= 0,
72 	IAVF_VSI_VMDQ1	= 1,
73 	IAVF_VSI_VMDQ2	= 2,
74 	IAVF_VSI_CTRL	= 3,
75 	IAVF_VSI_FCOE	= 4,
76 	IAVF_VSI_MIRROR	= 5,
77 	IAVF_VSI_SRIOV	= 6,
78 	IAVF_VSI_FDIR	= 7,
79 	IAVF_VSI_TYPE_UNKNOWN
80 };
81 
82 enum iavf_queue_type {
83 	IAVF_QUEUE_TYPE_RX = 0,
84 	IAVF_QUEUE_TYPE_TX,
85 	IAVF_QUEUE_TYPE_PE_CEQ,
86 	IAVF_QUEUE_TYPE_UNKNOWN
87 };
88 
89 #define IAVF_HW_CAP_MAX_GPIO		30
90 /* Capabilities of a PF or a VF or the whole device */
91 struct iavf_hw_capabilities {
92 	bool dcb;
93 	bool fcoe;
94 	u32 num_vsis;
95 	u32 num_rx_qp;
96 	u32 num_tx_qp;
97 	u32 base_queue;
98 	u32 num_msix_vectors_vf;
99 };
100 
101 struct iavf_mac_info {
102 	u8 addr[ETH_ALEN];
103 	u8 perm_addr[ETH_ALEN];
104 };
105 
106 /* PCI bus types */
107 enum iavf_bus_type {
108 	iavf_bus_type_unknown = 0,
109 	iavf_bus_type_pci,
110 	iavf_bus_type_pcix,
111 	iavf_bus_type_pci_express,
112 	iavf_bus_type_reserved
113 };
114 
115 /* PCI bus speeds */
116 enum iavf_bus_speed {
117 	iavf_bus_speed_unknown	= 0,
118 	iavf_bus_speed_33	= 33,
119 	iavf_bus_speed_66	= 66,
120 	iavf_bus_speed_100	= 100,
121 	iavf_bus_speed_120	= 120,
122 	iavf_bus_speed_133	= 133,
123 	iavf_bus_speed_2500	= 2500,
124 	iavf_bus_speed_5000	= 5000,
125 	iavf_bus_speed_8000	= 8000,
126 	iavf_bus_speed_reserved
127 };
128 
129 /* PCI bus widths */
130 enum iavf_bus_width {
131 	iavf_bus_width_unknown	= 0,
132 	iavf_bus_width_pcie_x1	= 1,
133 	iavf_bus_width_pcie_x2	= 2,
134 	iavf_bus_width_pcie_x4	= 4,
135 	iavf_bus_width_pcie_x8	= 8,
136 	iavf_bus_width_32	= 32,
137 	iavf_bus_width_64	= 64,
138 	iavf_bus_width_reserved
139 };
140 
141 /* Bus parameters */
142 struct iavf_bus_info {
143 	enum iavf_bus_speed speed;
144 	enum iavf_bus_width width;
145 	enum iavf_bus_type type;
146 
147 	u16 func;
148 	u16 device;
149 	u16 lan_id;
150 	u16 bus_id;
151 };
152 
153 #define IAVF_MAX_USER_PRIORITY		8
154 /* Port hardware description */
155 struct iavf_hw {
156 	u8 __iomem *hw_addr;
157 	void *back;
158 
159 	/* subsystem structs */
160 	struct iavf_mac_info mac;
161 	struct iavf_bus_info bus;
162 
163 	/* pci info */
164 	u16 device_id;
165 	u16 vendor_id;
166 	u16 subsystem_device_id;
167 	u16 subsystem_vendor_id;
168 	u8 revision_id;
169 
170 	/* capabilities for entire device and PCI func */
171 	struct iavf_hw_capabilities dev_caps;
172 
173 	/* Admin Queue info */
174 	struct iavf_adminq_info aq;
175 
176 	/* debug mask */
177 	u32 debug_mask;
178 	char err_str[16];
179 };
180 
181 /* RX Descriptors */
182 union iavf_16byte_rx_desc {
183 	struct {
184 		__le64 pkt_addr; /* Packet buffer address */
185 		__le64 hdr_addr; /* Header buffer address */
186 	} read;
187 	struct {
188 		struct {
189 			struct {
190 				union {
191 					__le16 mirroring_status;
192 					__le16 fcoe_ctx_id;
193 				} mirr_fcoe;
194 				__le16 l2tag1;
195 			} lo_dword;
196 			union {
197 				__le32 rss; /* RSS Hash */
198 				__le32 fd_id; /* Flow director filter id */
199 				__le32 fcoe_param; /* FCoE DDP Context id */
200 			} hi_dword;
201 		} qword0;
202 		struct {
203 			/* ext status/error/pktype/length */
204 			__le64 status_error_len;
205 		} qword1;
206 	} wb;  /* writeback */
207 };
208 
209 union iavf_32byte_rx_desc {
210 	struct {
211 		__le64  pkt_addr; /* Packet buffer address */
212 		__le64  hdr_addr; /* Header buffer address */
213 			/* bit 0 of hdr_buffer_addr is DD bit */
214 		__le64  rsvd1;
215 		__le64  rsvd2;
216 	} read;
217 	struct {
218 		struct {
219 			struct {
220 				union {
221 					__le16 mirroring_status;
222 					__le16 fcoe_ctx_id;
223 				} mirr_fcoe;
224 				__le16 l2tag1;
225 			} lo_dword;
226 			union {
227 				__le32 rss; /* RSS Hash */
228 				__le32 fcoe_param; /* FCoE DDP Context id */
229 				/* Flow director filter id in case of
230 				 * Programming status desc WB
231 				 */
232 				__le32 fd_id;
233 			} hi_dword;
234 		} qword0;
235 		struct {
236 			/* status/error/pktype/length */
237 			__le64 status_error_len;
238 		} qword1;
239 		struct {
240 			__le16 ext_status; /* extended status */
241 			__le16 rsvd;
242 			__le16 l2tag2_1;
243 			__le16 l2tag2_2;
244 		} qword2;
245 		struct {
246 			union {
247 				__le32 flex_bytes_lo;
248 				__le32 pe_status;
249 			} lo_dword;
250 			union {
251 				__le32 flex_bytes_hi;
252 				__le32 fd_id;
253 			} hi_dword;
254 		} qword3;
255 	} wb;  /* writeback */
256 };
257 
258 enum iavf_rx_desc_status_bits {
259 	/* Note: These are predefined bit offsets */
260 	IAVF_RX_DESC_STATUS_DD_SHIFT		= 0,
261 	IAVF_RX_DESC_STATUS_EOF_SHIFT		= 1,
262 	IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT	= 2,
263 	IAVF_RX_DESC_STATUS_L3L4P_SHIFT		= 3,
264 	IAVF_RX_DESC_STATUS_CRCP_SHIFT		= 4,
265 	IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT	= 5, /* 2 BITS */
266 	IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT	= 7,
267 	/* Note: Bit 8 is reserved in X710 and XL710 */
268 	IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT	= 8,
269 	IAVF_RX_DESC_STATUS_UMBCAST_SHIFT	= 9, /* 2 BITS */
270 	IAVF_RX_DESC_STATUS_FLM_SHIFT		= 11,
271 	IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT	= 12, /* 2 BITS */
272 	IAVF_RX_DESC_STATUS_LPBK_SHIFT		= 14,
273 	IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT	= 15,
274 	IAVF_RX_DESC_STATUS_RESERVED_SHIFT	= 16, /* 2 BITS */
275 	/* Note: For non-tunnel packets INT_UDP_0 is the right status for
276 	 * UDP header
277 	 */
278 	IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT	= 18,
279 	IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */
280 };
281 
282 #define IAVF_RXD_QW1_STATUS_SHIFT	0
283 #define IAVF_RXD_QW1_STATUS_MASK	((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \
284 					 << IAVF_RXD_QW1_STATUS_SHIFT)
285 
286 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
287 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK  (0x3UL << \
288 					    IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
289 
290 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
291 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK \
292 				    BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
293 
294 enum iavf_rx_desc_fltstat_values {
295 	IAVF_RX_DESC_FLTSTAT_NO_DATA	= 0,
296 	IAVF_RX_DESC_FLTSTAT_RSV_FD_ID	= 1, /* 16byte desc? FD_ID : RSV */
297 	IAVF_RX_DESC_FLTSTAT_RSV	= 2,
298 	IAVF_RX_DESC_FLTSTAT_RSS_HASH	= 3,
299 };
300 
301 #define IAVF_RXD_QW1_ERROR_SHIFT	19
302 #define IAVF_RXD_QW1_ERROR_MASK		(0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT)
303 
304 enum iavf_rx_desc_error_bits {
305 	/* Note: These are predefined bit offsets */
306 	IAVF_RX_DESC_ERROR_RXE_SHIFT		= 0,
307 	IAVF_RX_DESC_ERROR_RECIPE_SHIFT		= 1,
308 	IAVF_RX_DESC_ERROR_HBO_SHIFT		= 2,
309 	IAVF_RX_DESC_ERROR_L3L4E_SHIFT		= 3, /* 3 BITS */
310 	IAVF_RX_DESC_ERROR_IPE_SHIFT		= 3,
311 	IAVF_RX_DESC_ERROR_L4E_SHIFT		= 4,
312 	IAVF_RX_DESC_ERROR_EIPE_SHIFT		= 5,
313 	IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT	= 6,
314 	IAVF_RX_DESC_ERROR_PPRS_SHIFT		= 7
315 };
316 
317 enum iavf_rx_desc_error_l3l4e_fcoe_masks {
318 	IAVF_RX_DESC_ERROR_L3L4E_NONE		= 0,
319 	IAVF_RX_DESC_ERROR_L3L4E_PROT		= 1,
320 	IAVF_RX_DESC_ERROR_L3L4E_FC		= 2,
321 	IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR	= 3,
322 	IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN	= 4
323 };
324 
325 #define IAVF_RXD_QW1_PTYPE_SHIFT	30
326 #define IAVF_RXD_QW1_PTYPE_MASK		(0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT)
327 
328 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT	38
329 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK	(0x3FFFULL << \
330 					 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT)
331 
332 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT	52
333 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK	(0x7FFULL << \
334 					 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT)
335 
336 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT	63
337 #define IAVF_RXD_QW1_LENGTH_SPH_MASK	BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
338 
339 enum iavf_rx_desc_ext_status_bits {
340 	/* Note: These are predefined bit offsets */
341 	IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT	= 0,
342 	IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT	= 1,
343 	IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT	= 2, /* 2 BITS */
344 	IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT	= 4, /* 2 BITS */
345 	IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT	= 9,
346 	IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT	= 10,
347 	IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT	= 11,
348 };
349 
350 enum iavf_rx_desc_pe_status_bits {
351 	/* Note: These are predefined bit offsets */
352 	IAVF_RX_DESC_PE_STATUS_QPID_SHIFT	= 0, /* 18 BITS */
353 	IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT	= 0, /* 16 BITS */
354 	IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT	= 16, /* 8 BITS */
355 	IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT	= 24,
356 	IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT	= 25,
357 	IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT	= 26,
358 	IAVF_RX_DESC_PE_STATUS_URG_SHIFT	= 27,
359 	IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT	= 28,
360 	IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT	= 29
361 };
362 
363 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT		38
364 #define IAVF_RX_PROG_STATUS_DESC_LENGTH			0x2000000
365 
366 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT	2
367 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK	(0x7UL << \
368 				IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
369 
370 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT	19
371 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK		(0x3FUL << \
372 				IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
373 
374 enum iavf_rx_prog_status_desc_status_bits {
375 	/* Note: These are predefined bit offsets */
376 	IAVF_RX_PROG_STATUS_DESC_DD_SHIFT	= 0,
377 	IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT	= 2 /* 3 BITS */
378 };
379 
380 enum iavf_rx_prog_status_desc_prog_id_masks {
381 	IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS	= 1,
382 	IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS	= 2,
383 	IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS	= 4,
384 };
385 
386 enum iavf_rx_prog_status_desc_error_bits {
387 	/* Note: These are predefined bit offsets */
388 	IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT	= 0,
389 	IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT	= 1,
390 	IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT	= 2,
391 	IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT	= 3
392 };
393 
394 /* TX Descriptor */
395 struct iavf_tx_desc {
396 	__le64 buffer_addr; /* Address of descriptor's data buf */
397 	__le64 cmd_type_offset_bsz;
398 };
399 
400 #define IAVF_TXD_QW1_DTYPE_SHIFT	0
401 #define IAVF_TXD_QW1_DTYPE_MASK		(0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
402 
403 enum iavf_tx_desc_dtype_value {
404 	IAVF_TX_DESC_DTYPE_DATA		= 0x0,
405 	IAVF_TX_DESC_DTYPE_NOP		= 0x1, /* same as Context desc */
406 	IAVF_TX_DESC_DTYPE_CONTEXT	= 0x1,
407 	IAVF_TX_DESC_DTYPE_FCOE_CTX	= 0x2,
408 	IAVF_TX_DESC_DTYPE_FILTER_PROG	= 0x8,
409 	IAVF_TX_DESC_DTYPE_DDP_CTX	= 0x9,
410 	IAVF_TX_DESC_DTYPE_FLEX_DATA	= 0xB,
411 	IAVF_TX_DESC_DTYPE_FLEX_CTX_1	= 0xC,
412 	IAVF_TX_DESC_DTYPE_FLEX_CTX_2	= 0xD,
413 	IAVF_TX_DESC_DTYPE_DESC_DONE	= 0xF
414 };
415 
416 #define IAVF_TXD_QW1_CMD_SHIFT	4
417 #define IAVF_TXD_QW1_CMD_MASK	(0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT)
418 
419 enum iavf_tx_desc_cmd_bits {
420 	IAVF_TX_DESC_CMD_EOP			= 0x0001,
421 	IAVF_TX_DESC_CMD_RS			= 0x0002,
422 	IAVF_TX_DESC_CMD_ICRC			= 0x0004,
423 	IAVF_TX_DESC_CMD_IL2TAG1		= 0x0008,
424 	IAVF_TX_DESC_CMD_DUMMY			= 0x0010,
425 	IAVF_TX_DESC_CMD_IIPT_NONIP		= 0x0000, /* 2 BITS */
426 	IAVF_TX_DESC_CMD_IIPT_IPV6		= 0x0020, /* 2 BITS */
427 	IAVF_TX_DESC_CMD_IIPT_IPV4		= 0x0040, /* 2 BITS */
428 	IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM		= 0x0060, /* 2 BITS */
429 	IAVF_TX_DESC_CMD_FCOET			= 0x0080,
430 	IAVF_TX_DESC_CMD_L4T_EOFT_UNK		= 0x0000, /* 2 BITS */
431 	IAVF_TX_DESC_CMD_L4T_EOFT_TCP		= 0x0100, /* 2 BITS */
432 	IAVF_TX_DESC_CMD_L4T_EOFT_SCTP		= 0x0200, /* 2 BITS */
433 	IAVF_TX_DESC_CMD_L4T_EOFT_UDP		= 0x0300, /* 2 BITS */
434 	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N		= 0x0000, /* 2 BITS */
435 	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T		= 0x0100, /* 2 BITS */
436 	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI	= 0x0200, /* 2 BITS */
437 	IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A		= 0x0300, /* 2 BITS */
438 };
439 
440 #define IAVF_TXD_QW1_OFFSET_SHIFT	16
441 #define IAVF_TXD_QW1_OFFSET_MASK	(0x3FFFFULL << \
442 					 IAVF_TXD_QW1_OFFSET_SHIFT)
443 
444 enum iavf_tx_desc_length_fields {
445 	/* Note: These are predefined bit offsets */
446 	IAVF_TX_DESC_LENGTH_MACLEN_SHIFT	= 0, /* 7 BITS */
447 	IAVF_TX_DESC_LENGTH_IPLEN_SHIFT		= 7, /* 7 BITS */
448 	IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT	= 14 /* 4 BITS */
449 };
450 
451 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT	34
452 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK	(0x3FFFULL << \
453 					 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)
454 
455 #define IAVF_TXD_QW1_L2TAG1_SHIFT	48
456 #define IAVF_TXD_QW1_L2TAG1_MASK	(0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT)
457 
458 /* Context descriptors */
459 struct iavf_tx_context_desc {
460 	__le32 tunneling_params;
461 	__le16 l2tag2;
462 	__le16 rsvd;
463 	__le64 type_cmd_tso_mss;
464 };
465 
466 #define IAVF_TXD_CTX_QW1_CMD_SHIFT	4
467 #define IAVF_TXD_CTX_QW1_CMD_MASK	(0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT)
468 
469 enum iavf_tx_ctx_desc_cmd_bits {
470 	IAVF_TX_CTX_DESC_TSO		= 0x01,
471 	IAVF_TX_CTX_DESC_TSYN		= 0x02,
472 	IAVF_TX_CTX_DESC_IL2TAG2	= 0x04,
473 	IAVF_TX_CTX_DESC_IL2TAG2_IL2H	= 0x08,
474 	IAVF_TX_CTX_DESC_SWTCH_NOTAG	= 0x00,
475 	IAVF_TX_CTX_DESC_SWTCH_UPLINK	= 0x10,
476 	IAVF_TX_CTX_DESC_SWTCH_LOCAL	= 0x20,
477 	IAVF_TX_CTX_DESC_SWTCH_VSI	= 0x30,
478 	IAVF_TX_CTX_DESC_SWPE		= 0x40
479 };
480 
481 /* Packet Classifier Types for filters */
482 enum iavf_filter_pctype {
483 	/* Note: Values 0-28 are reserved for future use.
484 	 * Value 29, 30, 32 are not supported on XL710 and X710.
485 	 */
486 	IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP	= 29,
487 	IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP	= 30,
488 	IAVF_FILTER_PCTYPE_NONF_IPV4_UDP		= 31,
489 	IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK	= 32,
490 	IAVF_FILTER_PCTYPE_NONF_IPV4_TCP		= 33,
491 	IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP		= 34,
492 	IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER		= 35,
493 	IAVF_FILTER_PCTYPE_FRAG_IPV4			= 36,
494 	/* Note: Values 37-38 are reserved for future use.
495 	 * Value 39, 40, 42 are not supported on XL710 and X710.
496 	 */
497 	IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP	= 39,
498 	IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP	= 40,
499 	IAVF_FILTER_PCTYPE_NONF_IPV6_UDP		= 41,
500 	IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK	= 42,
501 	IAVF_FILTER_PCTYPE_NONF_IPV6_TCP		= 43,
502 	IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP		= 44,
503 	IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER		= 45,
504 	IAVF_FILTER_PCTYPE_FRAG_IPV6			= 46,
505 	/* Note: Value 47 is reserved for future use */
506 	IAVF_FILTER_PCTYPE_FCOE_OX			= 48,
507 	IAVF_FILTER_PCTYPE_FCOE_RX			= 49,
508 	IAVF_FILTER_PCTYPE_FCOE_OTHER			= 50,
509 	/* Note: Values 51-62 are reserved for future use */
510 	IAVF_FILTER_PCTYPE_L2_PAYLOAD			= 63,
511 };
512 
513 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT	30
514 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK	(0x3FFFFULL << \
515 					 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
516 
517 #define IAVF_TXD_CTX_QW1_MSS_SHIFT	50
518 #define IAVF_TXD_CTX_QW1_MSS_MASK	(0x3FFFULL << \
519 					 IAVF_TXD_CTX_QW1_MSS_SHIFT)
520 
521 #define IAVF_TXD_CTX_QW1_VSI_SHIFT	50
522 #define IAVF_TXD_CTX_QW1_VSI_MASK	(0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
523 
524 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT	0
525 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK	(0x3ULL << \
526 					 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
527 
528 enum iavf_tx_ctx_desc_eipt_offload {
529 	IAVF_TX_CTX_EXT_IP_NONE		= 0x0,
530 	IAVF_TX_CTX_EXT_IP_IPV6		= 0x1,
531 	IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM	= 0x2,
532 	IAVF_TX_CTX_EXT_IP_IPV4		= 0x3
533 };
534 
535 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT	2
536 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK	(0x3FULL << \
537 					 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
538 
539 #define IAVF_TXD_CTX_QW0_NATT_SHIFT	9
540 #define IAVF_TXD_CTX_QW0_NATT_MASK	(0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
541 
542 #define IAVF_TXD_CTX_UDP_TUNNELING	BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
543 #define IAVF_TXD_CTX_GRE_TUNNELING	(0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
544 
545 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT	11
546 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \
547 				       BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
548 
549 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST	IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
550 
551 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT	12
552 #define IAVF_TXD_CTX_QW0_NATLEN_MASK	(0X7FULL << \
553 					 IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
554 
555 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT	19
556 #define IAVF_TXD_CTX_QW0_DECTTL_MASK	(0xFULL << \
557 					 IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
558 
559 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT	23
560 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK	BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
561 
562 /* Statistics collected by each port, VSI, VEB, and S-channel */
563 struct iavf_eth_stats {
564 	u64 rx_bytes;			/* gorc */
565 	u64 rx_unicast;			/* uprc */
566 	u64 rx_multicast;		/* mprc */
567 	u64 rx_broadcast;		/* bprc */
568 	u64 rx_discards;		/* rdpc */
569 	u64 rx_unknown_protocol;	/* rupp */
570 	u64 tx_bytes;			/* gotc */
571 	u64 tx_unicast;			/* uptc */
572 	u64 tx_multicast;		/* mptc */
573 	u64 tx_broadcast;		/* bptc */
574 	u64 tx_discards;		/* tdpc */
575 	u64 tx_errors;			/* tepc */
576 };
577 #endif /* _IAVF_TYPE_H_ */
578