| /linux/drivers/pinctrl/renesas/ |
| H A D | pfc-r8a77970.c | 56 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
175 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(… macro
272 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
439 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
440 PINMUX_IPSR_GPSR(IP1_15_12, A11),
441 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
2247 IP1_15_12
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| H A D | pfc-r8a77980.c | 58 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
209 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F… macro
322 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
515 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
516 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
517 PINMUX_IPSR_GPSR(IP1_15_12, A11),
2701 IP1_15_12
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| H A D | pfc-r8a77995.c | 84 #define GPSR1_4 F_(DU_DB4, IP1_15_12)
221 #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)… macro
363 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
577 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
578 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
579 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
2688 IP1_15_12
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| H A D | pfc-r8a77965.c | 144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCL… macro
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
722 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
723 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
[all …]
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| H A D | pfc-r8a77951.c | 139 #define GPSR2_5 F_(IRQ5, IP1_15_12)
265 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCL… macro
448 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
711 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
712 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
713 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
714 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
715 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
716 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
717 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
[all …]
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| H A D | pfc-r8a7796.c | 144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0… macro
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
716 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
717 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
718 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
719 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
720 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
5317 IP1_15_12
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| H A D | pfc-r8a77990.c | 126 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
225 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) … macro
389 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
601 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
602 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
603 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
604 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
4803 IP1_15_12
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| H A D | pfc-r8a77470.c | 588 PINMUX_IPSR_GPSR(IP1_15_12, D1),
589 PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
590 PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
591 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
592 PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
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