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Searched refs:L3 (Results 1 – 25 of 110) sorted by relevance

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/linux/net/l3mdev/
H A DKconfig3 # Configuration for L3 master device support
7 bool "L3 Master device support"
11 drivers to support L3 master devices like VRF.
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,osm-l3.yaml7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
/linux/arch/x86/events/intel/
H A Dds.c94 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
96 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
111 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
112 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
113 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
134 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in __intel_pmu_pebs_data_source_grt()
135 data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in __intel_pmu_pebs_data_source_grt()
136 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); in __intel_pmu_pebs_data_source_grt()
159 data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); in __intel_pmu_pebs_data_source_cmt()
160 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in __intel_pmu_pebs_data_source_cmt()
[all …]
/linux/Documentation/networking/
H A Dipvlan.rst13 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
42 L3 bridge mode::
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
64 that in L3 mode the slaves won't receive any multicast / broadcast traffic.
65 L3 mode is more restrictive since routing is controlled from the other (mostly)
76 4.2 L3 mode:
79 In this mode TX processing up to L3 happens on the stack instance attached
88 This is very similar to the L3 mode except that iptables (conn-tracking)
89 works in this mode and hence it is L3-symmetric (L3s). This will have slightly less
90 performance but that shouldn't matter since you are choosing this mode over plain-L3
H A Dbareudp.rst7 There are various L3 encapsulation standards using UDP being discussed to
11 The Bareudp tunnel module provides a generic L3 encapsulation support for
12 tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel.
30 This creates a bareudp tunnel device which tunnels L3 traffic with ethertype
/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-cpus.dtsi170 next-level-cache = <&L3>;
178 next-level-cache = <&L3>;
186 next-level-cache = <&L3>;
194 next-level-cache = <&L3>;
197 L3: l3-cache { label
/linux/Documentation/devicetree/bindings/edac/
H A Dapm-xgene-edac.txt8 L3 - L3 cache controller
24 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
39 Required properties for L3 subnode:
42 - reg : First resource shall be the L3 EDAC resource.
/linux/Documentation/arch/x86/
H A Dresctrl.rst53 L2 and L3 CDP are controlled separately.
272 # echo L3:0=f7 > schemata
604 Memory b/w domain is L3 cache.
612 Memory bandwidth domain is L3 cache.
664 L3:0=ffff;1=ffff;2=ffff;3=ffff
669 L3:0=ffff;1=ffff;2=ffff;3=ffff
683 L3:0=ffff;1=ffff;2=ffff;3=ffff
689 L3:0=ffff;1=ffff;2=ffff;3=ffff
920 of L3 cache on socket 0.
951 # echo "L3:0=7c00;1=fffff" > p1/schemata
[all …]
/linux/arch/powerpc/perf/
H A Disa207-common.c229 ret = PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
264 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
266 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in isa207_find_source()
273 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
275 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
/linux/Documentation/admin-guide/perf/
H A Dqcom_l3_pmu.rst2 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
H A Darm_dsu_pmu.rst5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
7 allows counting the various events related to the L3 cache, Snoop Control Unit
/linux/Documentation/devicetree/bindings/sound/
H A Domap-dmic.txt7 <L3 interconnect address, size>;
16 <0x4902e000 0x7f>; /* L3 Interconnect */
H A Dti,omap4-mcpdm.yaml22 - description: L3 interconnect address
65 <0x49032000 0x7f>; /* L3 Interconnect */
/linux/drivers/net/ethernet/intel/libie/
H A Drx.c39 #define LIBIE_RX_PT_L3 __LIBIE_RX_PT_L2(NONE, L3)
42 LIBIE_RX_PT(IPV##oip, FRAG, NONE, NONE, NOT_FRAG, NONE, L3)
44 LIBIE_RX_PT(IPV##oip, NOT_FRAG, tun, teprot, tefr, NONE, L3)
/linux/drivers/perf/
H A DKconfig115 an L3 memory system. The L3 cache events are added into perf event
116 subsystem, allowing monitoring of various L3 cache perf events.
161 Unit (DSU). The DSU integrates one or more cores with an L3 memory
192 bool "Qualcomm Technologies L3-cache PMU"
196 Provides support for the L3 cache performance monitor unit (PMU)
198 Adds the L3 cache PMU into the perf events subsystem for
199 monitoring L3 cache events.
208 The SoC has PMU support in its L3 cache controller (L3C) and
/linux/Documentation/devicetree/bindings/arm/omap/
H A Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
/linux/arch/alpha/kernel/
H A Dsetup.c1196 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1207 L3 = -1; in determine_cpu_caches()
1228 L3 = -1; in determine_cpu_caches()
1259 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1273 L3 = -1; in determine_cpu_caches()
1296 L3 = -1; in determine_cpu_caches()
1303 L3 = -1; in determine_cpu_caches()
1308 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1315 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/linux/arch/m68k/lib/
H A Ddivsi3.S117 jpl L3
120 L3: movel sp@+, d2 label
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dmemory.txt88 | | | | +-> [20:12] L3 索引
103 | | | +----------> [28:16] L3 索引
/linux/arch/riscv/lib/
H A Dtishift.S33 beqz a2, .L3
44 .L3: label
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dmemory.txt92 | | | | +-> [20:12] L3 索引
107 | | | +----------> [28:16] L3 索引
/linux/lib/
H A Dtest_dynamic_debug.c92 enum cat_level_names { L0 = 22, L1, L2, L3, L4, L5, L6, L7 }; enumerator
135 prdbg(L3); in do_levels()
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
145 <0x49024000 0xff>; /* L3 Interconnect */
180 <0x49026000 0xff>; /* L3 Interconnect */
216 <0x4902a000 0x1000>; /* L3 data port */
252 <0x4902e000 0x7f>; /* L3 Interconnect */
314 <0x49032000 0x7f>; /* L3 Interconnect */
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-wbd111.dts45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c110 L0, L1, L2, L3, L4, enumerator
128 {0, L3, 200*1000},
157 [L3] = {
367 if (index >= L3) in s5pv210_target()

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