xref: /linux/drivers/mtd/nand/raw/lpc32xx_mlc.c (revision a503f91a)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Driver for NAND MLC Controller in LPC32xx
4  *
5  * Author: Roland Stigge <stigge@antcom.de>
6  *
7  * Copyright © 2011 WORK Microwave GmbH
8  * Copyright © 2011, 2012 Roland Stigge
9  *
10  * NAND Flash Controller Operation:
11  * - Read: Auto Decode
12  * - Write: Auto Encode
13  * - Tested Page Sizes: 2048, 4096
14  */
15 
16 #include <linux/slab.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/rawnand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/delay.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/of.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/mtd/lpc32xx_mlc.h>
30 #include <linux/io.h>
31 #include <linux/mm.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34 
35 #define DRV_NAME "lpc32xx_mlc"
36 
37 /**********************************************************************
38 * MLC NAND controller register offsets
39 **********************************************************************/
40 
41 #define MLC_BUFF(x)			(x + 0x00000)
42 #define MLC_DATA(x)			(x + 0x08000)
43 #define MLC_CMD(x)			(x + 0x10000)
44 #define MLC_ADDR(x)			(x + 0x10004)
45 #define MLC_ECC_ENC_REG(x)		(x + 0x10008)
46 #define MLC_ECC_DEC_REG(x)		(x + 0x1000C)
47 #define MLC_ECC_AUTO_ENC_REG(x)		(x + 0x10010)
48 #define MLC_ECC_AUTO_DEC_REG(x)		(x + 0x10014)
49 #define MLC_RPR(x)			(x + 0x10018)
50 #define MLC_WPR(x)			(x + 0x1001C)
51 #define MLC_RUBP(x)			(x + 0x10020)
52 #define MLC_ROBP(x)			(x + 0x10024)
53 #define MLC_SW_WP_ADD_LOW(x)		(x + 0x10028)
54 #define MLC_SW_WP_ADD_HIG(x)		(x + 0x1002C)
55 #define MLC_ICR(x)			(x + 0x10030)
56 #define MLC_TIME_REG(x)			(x + 0x10034)
57 #define MLC_IRQ_MR(x)			(x + 0x10038)
58 #define MLC_IRQ_SR(x)			(x + 0x1003C)
59 #define MLC_LOCK_PR(x)			(x + 0x10044)
60 #define MLC_ISR(x)			(x + 0x10048)
61 #define MLC_CEH(x)			(x + 0x1004C)
62 
63 /**********************************************************************
64 * MLC_CMD bit definitions
65 **********************************************************************/
66 #define MLCCMD_RESET			0xFF
67 
68 /**********************************************************************
69 * MLC_ICR bit definitions
70 **********************************************************************/
71 #define MLCICR_WPROT			(1 << 3)
72 #define MLCICR_LARGEBLOCK		(1 << 2)
73 #define MLCICR_LONGADDR			(1 << 1)
74 #define MLCICR_16BIT			(1 << 0)  /* unsupported by LPC32x0! */
75 
76 /**********************************************************************
77 * MLC_TIME_REG bit definitions
78 **********************************************************************/
79 #define MLCTIMEREG_TCEA_DELAY(n)	(((n) & 0x03) << 24)
80 #define MLCTIMEREG_BUSY_DELAY(n)	(((n) & 0x1F) << 19)
81 #define MLCTIMEREG_NAND_TA(n)		(((n) & 0x07) << 16)
82 #define MLCTIMEREG_RD_HIGH(n)		(((n) & 0x0F) << 12)
83 #define MLCTIMEREG_RD_LOW(n)		(((n) & 0x0F) << 8)
84 #define MLCTIMEREG_WR_HIGH(n)		(((n) & 0x0F) << 4)
85 #define MLCTIMEREG_WR_LOW(n)		(((n) & 0x0F) << 0)
86 
87 /**********************************************************************
88 * MLC_IRQ_MR and MLC_IRQ_SR bit definitions
89 **********************************************************************/
90 #define MLCIRQ_NAND_READY		(1 << 5)
91 #define MLCIRQ_CONTROLLER_READY		(1 << 4)
92 #define MLCIRQ_DECODE_FAILURE		(1 << 3)
93 #define MLCIRQ_DECODE_ERROR		(1 << 2)
94 #define MLCIRQ_ECC_READY		(1 << 1)
95 #define MLCIRQ_WRPROT_FAULT		(1 << 0)
96 
97 /**********************************************************************
98 * MLC_LOCK_PR bit definitions
99 **********************************************************************/
100 #define MLCLOCKPR_MAGIC			0xA25E
101 
102 /**********************************************************************
103 * MLC_ISR bit definitions
104 **********************************************************************/
105 #define MLCISR_DECODER_FAILURE		(1 << 6)
106 #define MLCISR_ERRORS			((1 << 4) | (1 << 5))
107 #define MLCISR_ERRORS_DETECTED		(1 << 3)
108 #define MLCISR_ECC_READY		(1 << 2)
109 #define MLCISR_CONTROLLER_READY		(1 << 1)
110 #define MLCISR_NAND_READY		(1 << 0)
111 
112 /**********************************************************************
113 * MLC_CEH bit definitions
114 **********************************************************************/
115 #define MLCCEH_NORMAL			(1 << 0)
116 
117 struct lpc32xx_nand_cfg_mlc {
118 	uint32_t tcea_delay;
119 	uint32_t busy_delay;
120 	uint32_t nand_ta;
121 	uint32_t rd_high;
122 	uint32_t rd_low;
123 	uint32_t wr_high;
124 	uint32_t wr_low;
125 	struct mtd_partition *parts;
126 	unsigned num_parts;
127 };
128 
lpc32xx_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)129 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
130 				 struct mtd_oob_region *oobregion)
131 {
132 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
133 
134 	if (section >= nand_chip->ecc.steps)
135 		return -ERANGE;
136 
137 	oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes;
138 	oobregion->length = nand_chip->ecc.bytes;
139 
140 	return 0;
141 }
142 
lpc32xx_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)143 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
144 				  struct mtd_oob_region *oobregion)
145 {
146 	struct nand_chip *nand_chip = mtd_to_nand(mtd);
147 
148 	if (section >= nand_chip->ecc.steps)
149 		return -ERANGE;
150 
151 	oobregion->offset = 16 * section;
152 	oobregion->length = 16 - nand_chip->ecc.bytes;
153 
154 	return 0;
155 }
156 
157 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
158 	.ecc = lpc32xx_ooblayout_ecc,
159 	.free = lpc32xx_ooblayout_free,
160 };
161 
162 static struct nand_bbt_descr lpc32xx_nand_bbt = {
163 	.options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
164 		   NAND_BBT_WRITE,
165 	.pages = { 524224, 0, 0, 0, 0, 0, 0, 0 },
166 };
167 
168 static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = {
169 	.options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
170 		   NAND_BBT_WRITE,
171 	.pages = { 524160, 0, 0, 0, 0, 0, 0, 0 },
172 };
173 
174 struct lpc32xx_nand_host {
175 	struct platform_device	*pdev;
176 	struct nand_chip	nand_chip;
177 	struct lpc32xx_mlc_platform_data *pdata;
178 	struct clk		*clk;
179 	struct gpio_desc	*wp_gpio;
180 	void __iomem		*io_base;
181 	int			irq;
182 	struct lpc32xx_nand_cfg_mlc	*ncfg;
183 	struct completion       comp_nand;
184 	struct completion       comp_controller;
185 	uint32_t llptr;
186 	/*
187 	 * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer
188 	 */
189 	dma_addr_t		oob_buf_phy;
190 	/*
191 	 * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer
192 	 */
193 	uint8_t			*oob_buf;
194 	/* Physical address of DMA base address */
195 	dma_addr_t		io_base_phy;
196 
197 	struct completion	comp_dma;
198 	struct dma_chan		*dma_chan;
199 	struct dma_slave_config	dma_slave_config;
200 	struct scatterlist	sgl;
201 	uint8_t			*dma_buf;
202 	uint8_t			*dummy_buf;
203 	int			mlcsubpages; /* number of 512bytes-subpages */
204 };
205 
206 /*
207  * Activate/Deactivate DMA Operation:
208  *
209  * Using the PL080 DMA Controller for transferring the 512 byte subpages
210  * instead of doing readl() / writel() in a loop slows it down significantly.
211  * Measurements via getnstimeofday() upon 512 byte subpage reads reveal:
212  *
213  * - readl() of 128 x 32 bits in a loop: ~20us
214  * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us
215  * - DMA read of 512 bytes (32 bit, no bursts): ~100us
216  *
217  * This applies to the transfer itself. In the DMA case: only the
218  * wait_for_completion() (DMA setup _not_ included).
219  *
220  * Note that the 512 bytes subpage transfer is done directly from/to a
221  * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a
222  * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND
223  * controller transferring data between its internal buffer to/from the NAND
224  * chip.)
225  *
226  * Therefore, using the PL080 DMA is disabled by default, for now.
227  *
228  */
229 static int use_dma;
230 
lpc32xx_nand_setup(struct lpc32xx_nand_host * host)231 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
232 {
233 	uint32_t clkrate, tmp;
234 
235 	/* Reset MLC controller */
236 	writel(MLCCMD_RESET, MLC_CMD(host->io_base));
237 	udelay(1000);
238 
239 	/* Get base clock for MLC block */
240 	clkrate = clk_get_rate(host->clk);
241 	if (clkrate == 0)
242 		clkrate = 104000000;
243 
244 	/* Unlock MLC_ICR
245 	 * (among others, will be locked again automatically) */
246 	writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
247 
248 	/* Configure MLC Controller: Large Block, 5 Byte Address */
249 	tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR;
250 	writel(tmp, MLC_ICR(host->io_base));
251 
252 	/* Unlock MLC_TIME_REG
253 	 * (among others, will be locked again automatically) */
254 	writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
255 
256 	/* Compute clock setup values, see LPC and NAND manual */
257 	tmp = 0;
258 	tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
259 	tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
260 	tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
261 	tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
262 	tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
263 	tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
264 	tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
265 	writel(tmp, MLC_TIME_REG(host->io_base));
266 
267 	/* Enable IRQ for CONTROLLER_READY and NAND_READY */
268 	writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY,
269 			MLC_IRQ_MR(host->io_base));
270 
271 	/* Normal nCE operation: nCE controlled by controller */
272 	writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
273 }
274 
275 /*
276  * Hardware specific access to control lines
277  */
lpc32xx_nand_cmd_ctrl(struct nand_chip * nand_chip,int cmd,unsigned int ctrl)278 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
279 				  unsigned int ctrl)
280 {
281 	struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
282 
283 	if (cmd != NAND_CMD_NONE) {
284 		if (ctrl & NAND_CLE)
285 			writel(cmd, MLC_CMD(host->io_base));
286 		else
287 			writel(cmd, MLC_ADDR(host->io_base));
288 	}
289 }
290 
291 /*
292  * Read Device Ready (NAND device _and_ controller ready)
293  */
lpc32xx_nand_device_ready(struct nand_chip * nand_chip)294 static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip)
295 {
296 	struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
297 
298 	if ((readb(MLC_ISR(host->io_base)) &
299 	     (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) ==
300 	    (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY))
301 		return  1;
302 
303 	return 0;
304 }
305 
lpc3xxx_nand_irq(int irq,void * data)306 static irqreturn_t lpc3xxx_nand_irq(int irq, void *data)
307 {
308 	struct lpc32xx_nand_host *host = data;
309 	uint8_t sr;
310 
311 	/* Clear interrupt flag by reading status */
312 	sr = readb(MLC_IRQ_SR(host->io_base));
313 	if (sr & MLCIRQ_NAND_READY)
314 		complete(&host->comp_nand);
315 	if (sr & MLCIRQ_CONTROLLER_READY)
316 		complete(&host->comp_controller);
317 
318 	return IRQ_HANDLED;
319 }
320 
lpc32xx_waitfunc_nand(struct nand_chip * chip)321 static int lpc32xx_waitfunc_nand(struct nand_chip *chip)
322 {
323 	struct mtd_info *mtd = nand_to_mtd(chip);
324 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
325 
326 	if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
327 		goto exit;
328 
329 	wait_for_completion(&host->comp_nand);
330 
331 	while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
332 		/* Seems to be delayed sometimes by controller */
333 		dev_dbg(&mtd->dev, "Warning: NAND not ready.\n");
334 		cpu_relax();
335 	}
336 
337 exit:
338 	return NAND_STATUS_READY;
339 }
340 
lpc32xx_waitfunc_controller(struct nand_chip * chip)341 static int lpc32xx_waitfunc_controller(struct nand_chip *chip)
342 {
343 	struct mtd_info *mtd = nand_to_mtd(chip);
344 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
345 
346 	if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
347 		goto exit;
348 
349 	wait_for_completion(&host->comp_controller);
350 
351 	while (!(readb(MLC_ISR(host->io_base)) &
352 		 MLCISR_CONTROLLER_READY)) {
353 		dev_dbg(&mtd->dev, "Warning: Controller not ready.\n");
354 		cpu_relax();
355 	}
356 
357 exit:
358 	return NAND_STATUS_READY;
359 }
360 
lpc32xx_waitfunc(struct nand_chip * chip)361 static int lpc32xx_waitfunc(struct nand_chip *chip)
362 {
363 	lpc32xx_waitfunc_nand(chip);
364 	lpc32xx_waitfunc_controller(chip);
365 
366 	return NAND_STATUS_READY;
367 }
368 
369 /*
370  * Enable NAND write protect
371  */
lpc32xx_wp_enable(struct lpc32xx_nand_host * host)372 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
373 {
374 	if (host->wp_gpio)
375 		gpiod_set_value_cansleep(host->wp_gpio, 1);
376 }
377 
378 /*
379  * Disable NAND write protect
380  */
lpc32xx_wp_disable(struct lpc32xx_nand_host * host)381 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
382 {
383 	if (host->wp_gpio)
384 		gpiod_set_value_cansleep(host->wp_gpio, 0);
385 }
386 
lpc32xx_dma_complete_func(void * completion)387 static void lpc32xx_dma_complete_func(void *completion)
388 {
389 	complete(completion);
390 }
391 
lpc32xx_xmit_dma(struct mtd_info * mtd,void * mem,int len,enum dma_transfer_direction dir)392 static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
393 			    enum dma_transfer_direction dir)
394 {
395 	struct nand_chip *chip = mtd_to_nand(mtd);
396 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
397 	struct dma_async_tx_descriptor *desc;
398 	int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
399 	int res;
400 
401 	sg_init_one(&host->sgl, mem, len);
402 
403 	res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
404 			 DMA_BIDIRECTIONAL);
405 	if (res != 1) {
406 		dev_err(mtd->dev.parent, "Failed to map sg list\n");
407 		return -ENXIO;
408 	}
409 	desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
410 				       flags);
411 	if (!desc) {
412 		dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
413 		goto out1;
414 	}
415 
416 	init_completion(&host->comp_dma);
417 	desc->callback = lpc32xx_dma_complete_func;
418 	desc->callback_param = &host->comp_dma;
419 
420 	dmaengine_submit(desc);
421 	dma_async_issue_pending(host->dma_chan);
422 
423 	wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
424 
425 	dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
426 		     DMA_BIDIRECTIONAL);
427 	return 0;
428 out1:
429 	dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
430 		     DMA_BIDIRECTIONAL);
431 	return -ENXIO;
432 }
433 
lpc32xx_read_page(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)434 static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,
435 			     int oob_required, int page)
436 {
437 	struct mtd_info *mtd = nand_to_mtd(chip);
438 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
439 	int i, j;
440 	uint8_t *oobbuf = chip->oob_poi;
441 	uint32_t mlc_isr;
442 	int res;
443 	uint8_t *dma_buf;
444 	bool dma_mapped;
445 
446 	if ((void *)buf <= high_memory) {
447 		dma_buf = buf;
448 		dma_mapped = true;
449 	} else {
450 		dma_buf = host->dma_buf;
451 		dma_mapped = false;
452 	}
453 
454 	/* Writing Command and Address */
455 	nand_read_page_op(chip, page, 0, NULL, 0);
456 
457 	/* For all sub-pages */
458 	for (i = 0; i < host->mlcsubpages; i++) {
459 		/* Start Auto Decode Command */
460 		writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
461 
462 		/* Wait for Controller Ready */
463 		lpc32xx_waitfunc_controller(chip);
464 
465 		/* Check ECC Error status */
466 		mlc_isr = readl(MLC_ISR(host->io_base));
467 		if (mlc_isr & MLCISR_DECODER_FAILURE) {
468 			mtd->ecc_stats.failed++;
469 			dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__);
470 		} else if (mlc_isr & MLCISR_ERRORS_DETECTED) {
471 			mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1;
472 		}
473 
474 		/* Read 512 + 16 Bytes */
475 		if (use_dma) {
476 			res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
477 					       DMA_DEV_TO_MEM);
478 			if (res)
479 				return res;
480 		} else {
481 			for (j = 0; j < (512 >> 2); j++) {
482 				*((uint32_t *)(buf)) =
483 					readl(MLC_BUFF(host->io_base));
484 				buf += 4;
485 			}
486 		}
487 		for (j = 0; j < (16 >> 2); j++) {
488 			*((uint32_t *)(oobbuf)) =
489 				readl(MLC_BUFF(host->io_base));
490 			oobbuf += 4;
491 		}
492 	}
493 
494 	if (use_dma && !dma_mapped)
495 		memcpy(buf, dma_buf, mtd->writesize);
496 
497 	return 0;
498 }
499 
lpc32xx_write_page_lowlevel(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)500 static int lpc32xx_write_page_lowlevel(struct nand_chip *chip,
501 				       const uint8_t *buf, int oob_required,
502 				       int page)
503 {
504 	struct mtd_info *mtd = nand_to_mtd(chip);
505 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
506 	const uint8_t *oobbuf = chip->oob_poi;
507 	uint8_t *dma_buf = (uint8_t *)buf;
508 	int res;
509 	int i, j;
510 
511 	if (use_dma && (void *)buf >= high_memory) {
512 		dma_buf = host->dma_buf;
513 		memcpy(dma_buf, buf, mtd->writesize);
514 	}
515 
516 	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
517 
518 	for (i = 0; i < host->mlcsubpages; i++) {
519 		/* Start Encode */
520 		writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
521 
522 		/* Write 512 + 6 Bytes to Buffer */
523 		if (use_dma) {
524 			res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
525 					       DMA_MEM_TO_DEV);
526 			if (res)
527 				return res;
528 		} else {
529 			for (j = 0; j < (512 >> 2); j++) {
530 				writel(*((uint32_t *)(buf)),
531 				       MLC_BUFF(host->io_base));
532 				buf += 4;
533 			}
534 		}
535 		writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
536 		oobbuf += 4;
537 		writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
538 		oobbuf += 12;
539 
540 		/* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */
541 		writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
542 
543 		/* Wait for Controller Ready */
544 		lpc32xx_waitfunc_controller(chip);
545 	}
546 
547 	return nand_prog_page_end_op(chip);
548 }
549 
lpc32xx_read_oob(struct nand_chip * chip,int page)550 static int lpc32xx_read_oob(struct nand_chip *chip, int page)
551 {
552 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
553 
554 	/* Read whole page - necessary with MLC controller! */
555 	lpc32xx_read_page(chip, host->dummy_buf, 1, page);
556 
557 	return 0;
558 }
559 
lpc32xx_write_oob(struct nand_chip * chip,int page)560 static int lpc32xx_write_oob(struct nand_chip *chip, int page)
561 {
562 	/* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */
563 	return 0;
564 }
565 
566 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
lpc32xx_ecc_enable(struct nand_chip * chip,int mode)567 static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode)
568 {
569 	/* Always enabled! */
570 }
571 
lpc32xx_dma_setup(struct lpc32xx_nand_host * host)572 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
573 {
574 	struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
575 	dma_cap_mask_t mask;
576 
577 	host->dma_chan = dma_request_chan(mtd->dev.parent, "rx-tx");
578 	if (IS_ERR(host->dma_chan)) {
579 		/* fallback to request using platform data */
580 		if (!host->pdata || !host->pdata->dma_filter) {
581 			dev_err(mtd->dev.parent, "no DMA platform data\n");
582 			return -ENOENT;
583 		}
584 
585 		dma_cap_zero(mask);
586 		dma_cap_set(DMA_SLAVE, mask);
587 		host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, "nand-mlc");
588 
589 		if (!host->dma_chan) {
590 			dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
591 			return -EBUSY;
592 		}
593 	}
594 
595 	/*
596 	 * Set direction to a sensible value even if the dmaengine driver
597 	 * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x
598 	 * driver criticizes it as "alien transfer direction".
599 	 */
600 	host->dma_slave_config.direction = DMA_DEV_TO_MEM;
601 	host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
602 	host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
603 	host->dma_slave_config.src_maxburst = 128;
604 	host->dma_slave_config.dst_maxburst = 128;
605 	/* DMA controller does flow control: */
606 	host->dma_slave_config.device_fc = false;
607 	host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
608 	host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
609 	if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
610 		dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
611 		goto out1;
612 	}
613 
614 	return 0;
615 out1:
616 	dma_release_channel(host->dma_chan);
617 	return -ENXIO;
618 }
619 
lpc32xx_parse_dt(struct device * dev)620 static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
621 {
622 	struct lpc32xx_nand_cfg_mlc *ncfg;
623 	struct device_node *np = dev->of_node;
624 
625 	ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
626 	if (!ncfg)
627 		return NULL;
628 
629 	of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay);
630 	of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay);
631 	of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta);
632 	of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high);
633 	of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low);
634 	of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high);
635 	of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low);
636 
637 	if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta ||
638 	    !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high ||
639 	    !ncfg->wr_low) {
640 		dev_err(dev, "chip parameters not specified correctly\n");
641 		return NULL;
642 	}
643 
644 	return ncfg;
645 }
646 
lpc32xx_nand_attach_chip(struct nand_chip * chip)647 static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
648 {
649 	struct mtd_info *mtd = nand_to_mtd(chip);
650 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
651 	struct device *dev = &host->pdev->dev;
652 
653 	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
654 		return 0;
655 
656 	host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
657 	if (!host->dma_buf)
658 		return -ENOMEM;
659 
660 	host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
661 	if (!host->dummy_buf)
662 		return -ENOMEM;
663 
664 	chip->ecc.size = 512;
665 	chip->ecc.hwctl = lpc32xx_ecc_enable;
666 	chip->ecc.read_page_raw = lpc32xx_read_page;
667 	chip->ecc.read_page = lpc32xx_read_page;
668 	chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
669 	chip->ecc.write_page = lpc32xx_write_page_lowlevel;
670 	chip->ecc.write_oob = lpc32xx_write_oob;
671 	chip->ecc.read_oob = lpc32xx_read_oob;
672 	chip->ecc.strength = 4;
673 	chip->ecc.bytes = 10;
674 
675 	mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
676 	host->mlcsubpages = mtd->writesize / 512;
677 
678 	return 0;
679 }
680 
681 static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
682 	.attach_chip = lpc32xx_nand_attach_chip,
683 };
684 
685 /*
686  * Probe for NAND controller
687  */
lpc32xx_nand_probe(struct platform_device * pdev)688 static int lpc32xx_nand_probe(struct platform_device *pdev)
689 {
690 	struct lpc32xx_nand_host *host;
691 	struct mtd_info *mtd;
692 	struct nand_chip *nand_chip;
693 	struct resource *rc;
694 	int res;
695 
696 	/* Allocate memory for the device structure (and zero it) */
697 	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
698 	if (!host)
699 		return -ENOMEM;
700 
701 	host->pdev = pdev;
702 
703 	host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc);
704 	if (IS_ERR(host->io_base))
705 		return PTR_ERR(host->io_base);
706 
707 	host->io_base_phy = rc->start;
708 
709 	nand_chip = &host->nand_chip;
710 	mtd = nand_to_mtd(nand_chip);
711 	if (pdev->dev.of_node)
712 		host->ncfg = lpc32xx_parse_dt(&pdev->dev);
713 	if (!host->ncfg) {
714 		dev_err(&pdev->dev,
715 			"Missing or bad NAND config from device tree\n");
716 		return -ENOENT;
717 	}
718 
719 	/* Start with WP disabled, if available */
720 	host->wp_gpio = gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW);
721 	res = PTR_ERR_OR_ZERO(host->wp_gpio);
722 	if (res) {
723 		if (res != -EPROBE_DEFER)
724 			dev_err(&pdev->dev, "WP GPIO is not available: %d\n",
725 				res);
726 		return res;
727 	}
728 
729 	gpiod_set_consumer_name(host->wp_gpio, "NAND WP");
730 
731 	host->pdata = dev_get_platdata(&pdev->dev);
732 
733 	/* link the private data structures */
734 	nand_set_controller_data(nand_chip, host);
735 	nand_set_flash_node(nand_chip, pdev->dev.of_node);
736 	mtd->dev.parent = &pdev->dev;
737 
738 	/* Get NAND clock */
739 	host->clk = clk_get(&pdev->dev, NULL);
740 	if (IS_ERR(host->clk)) {
741 		dev_err(&pdev->dev, "Clock initialization failure\n");
742 		res = -ENOENT;
743 		goto free_gpio;
744 	}
745 	res = clk_prepare_enable(host->clk);
746 	if (res)
747 		goto put_clk;
748 
749 	nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
750 	nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
751 	nand_chip->legacy.chip_delay = 25; /* us */
752 	nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
753 	nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
754 
755 	/* Init NAND controller */
756 	lpc32xx_nand_setup(host);
757 
758 	platform_set_drvdata(pdev, host);
759 
760 	/* Initialize function pointers */
761 	nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
762 
763 	nand_chip->options = NAND_NO_SUBPAGE_WRITE;
764 	nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
765 	nand_chip->bbt_td = &lpc32xx_nand_bbt;
766 	nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
767 
768 	if (use_dma) {
769 		res = lpc32xx_dma_setup(host);
770 		if (res) {
771 			res = -EIO;
772 			goto unprepare_clk;
773 		}
774 	}
775 
776 	/* initially clear interrupt status */
777 	readb(MLC_IRQ_SR(host->io_base));
778 
779 	init_completion(&host->comp_nand);
780 	init_completion(&host->comp_controller);
781 
782 	host->irq = platform_get_irq(pdev, 0);
783 	if (host->irq < 0) {
784 		res = -EINVAL;
785 		goto release_dma_chan;
786 	}
787 
788 	if (request_irq(host->irq, &lpc3xxx_nand_irq,
789 			IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
790 		dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
791 		res = -ENXIO;
792 		goto release_dma_chan;
793 	}
794 
795 	/*
796 	 * Scan to find existence of the device and get the type of NAND device:
797 	 * SMALL block or LARGE block.
798 	 */
799 	nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
800 	res = nand_scan(nand_chip, 1);
801 	if (res)
802 		goto free_irq;
803 
804 	mtd->name = DRV_NAME;
805 
806 	res = mtd_device_register(mtd, host->ncfg->parts,
807 				  host->ncfg->num_parts);
808 	if (res)
809 		goto cleanup_nand;
810 
811 	return 0;
812 
813 cleanup_nand:
814 	nand_cleanup(nand_chip);
815 free_irq:
816 	free_irq(host->irq, host);
817 release_dma_chan:
818 	if (use_dma)
819 		dma_release_channel(host->dma_chan);
820 unprepare_clk:
821 	clk_disable_unprepare(host->clk);
822 put_clk:
823 	clk_put(host->clk);
824 free_gpio:
825 	lpc32xx_wp_enable(host);
826 	gpiod_put(host->wp_gpio);
827 
828 	return res;
829 }
830 
831 /*
832  * Remove NAND device
833  */
lpc32xx_nand_remove(struct platform_device * pdev)834 static void lpc32xx_nand_remove(struct platform_device *pdev)
835 {
836 	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
837 	struct nand_chip *chip = &host->nand_chip;
838 	int ret;
839 
840 	ret = mtd_device_unregister(nand_to_mtd(chip));
841 	WARN_ON(ret);
842 	nand_cleanup(chip);
843 
844 	free_irq(host->irq, host);
845 	if (use_dma)
846 		dma_release_channel(host->dma_chan);
847 
848 	clk_disable_unprepare(host->clk);
849 	clk_put(host->clk);
850 
851 	lpc32xx_wp_enable(host);
852 	gpiod_put(host->wp_gpio);
853 }
854 
lpc32xx_nand_resume(struct platform_device * pdev)855 static int lpc32xx_nand_resume(struct platform_device *pdev)
856 {
857 	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
858 	int ret;
859 
860 	/* Re-enable NAND clock */
861 	ret = clk_prepare_enable(host->clk);
862 	if (ret)
863 		return ret;
864 
865 	/* Fresh init of NAND controller */
866 	lpc32xx_nand_setup(host);
867 
868 	/* Disable write protect */
869 	lpc32xx_wp_disable(host);
870 
871 	return 0;
872 }
873 
lpc32xx_nand_suspend(struct platform_device * pdev,pm_message_t pm)874 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
875 {
876 	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
877 
878 	/* Enable write protect for safety */
879 	lpc32xx_wp_enable(host);
880 
881 	/* Disable clock */
882 	clk_disable_unprepare(host->clk);
883 	return 0;
884 }
885 
886 static const struct of_device_id lpc32xx_nand_match[] = {
887 	{ .compatible = "nxp,lpc3220-mlc" },
888 	{ /* sentinel */ },
889 };
890 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
891 
892 static struct platform_driver lpc32xx_nand_driver = {
893 	.probe		= lpc32xx_nand_probe,
894 	.remove_new	= lpc32xx_nand_remove,
895 	.resume		= pm_ptr(lpc32xx_nand_resume),
896 	.suspend	= pm_ptr(lpc32xx_nand_suspend),
897 	.driver		= {
898 		.name	= DRV_NAME,
899 		.of_match_table = lpc32xx_nand_match,
900 	},
901 };
902 
903 module_platform_driver(lpc32xx_nand_driver);
904 
905 MODULE_LICENSE("GPL");
906 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
907 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller");
908