1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_PHY_H__
6 #define __RTW89_PHY_H__
7
8 #include "core.h"
9
10 #define RTW89_BBMCU_ADDR_OFFSET 0x30000
11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16)
12
13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)
14 #define PHY_HEADLINE_VALID 0xf
15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)
16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \
17 FIELD_PREP(GENMASK(7, 0), cv))
18
19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)
20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)
21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)
22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)
23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
24 #define PHY_COND_BRANCH_IF 0x8
25 #define PHY_COND_BRANCH_ELIF 0x9
26 #define PHY_COND_BRANCH_ELSE 0xa
27 #define PHY_COND_BRANCH_END 0xb
28 #define PHY_COND_CHECK 0x4
29 #define PHY_COND_DONT_CARE 0xff
30
31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
33 #define RA_MASK_SUBCCK_RATES 0x5ULL
34 #define RA_MASK_SUBOFDM_RATES 0x10ULL
35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)
41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)
42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)
43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48)
44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)
45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)
46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)
47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36)
48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48)
49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12)
50 #define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12)
51 #define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28)
52 #define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44)
53 #define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60)
54 #define RA_MASK_EHT_RATES GENMASK_ULL(62, 12)
55
56 #define CFO_TRK_ENABLE_TH (2 << 2)
57 #define CFO_TRK_STOP_TH_4 (30 << 2)
58 #define CFO_TRK_STOP_TH_3 (20 << 2)
59 #define CFO_TRK_STOP_TH_2 (10 << 2)
60 #define CFO_TRK_STOP_TH_1 (00 << 2)
61 #define CFO_TRK_STOP_TH (2 << 2)
62 #define CFO_SW_COMP_FINE_TUNE (2 << 2)
63 #define CFO_PERIOD_CNT 15
64 #define CFO_BOUND 64
65 #define CFO_TP_UPPER 100
66 #define CFO_TP_LOWER 50
67 #define CFO_COMP_PERIOD 250
68 #define CFO_COMP_WEIGHT 8
69 #define MAX_CFO_TOLERANCE 30
70 #define CFO_TF_CNT_TH 300
71
72 #define UL_TB_TF_CNT_L2H_TH 100
73 #define UL_TB_TF_CNT_H2L_TH 70
74
75 #define ANTDIV_TRAINNING_CNT 2
76 #define ANTDIV_TRAINNING_INTVL 30
77 #define ANTDIV_DELAY 110
78 #define ANTDIV_TP_DIFF_TH_HIGH 100
79 #define ANTDIV_TP_DIFF_TH_LOW 5
80 #define ANTDIV_EVM_DIFF_TH 8
81 #define ANTDIV_RSSI_DIFF_TH 3
82
83 #define CCX_MAX_PERIOD 2097
84 #define CCX_MAX_PERIOD_UNIT 32
85 #define MS_TO_4US_RATIO 250
86 #define ENV_MNTR_FAIL_DWORD 0xffffffff
87 #define ENV_MNTR_IFSCLM_HIS_MAX 127
88 #define PERMIL 1000
89 #define PERCENT 100
90 #define IFS_CLM_TH0_UPPER 64
91 #define IFS_CLM_TH_MUL 4
92 #define IFS_CLM_TH_START_IDX 0
93
94 #define TIA0_GAIN_A 12
95 #define TIA0_GAIN_G 16
96 #define LNA0_GAIN (-24)
97 #define U4_MAX_BIT 3
98 #define U8_MAX_BIT 7
99 #define DIG_GAIN_SHIFT 2
100 #define DIG_GAIN 8
101
102 #define LNA_IDX_MAX 6
103 #define LNA_IDX_MIN 0
104 #define TIA_IDX_MAX 1
105 #define TIA_IDX_MIN 0
106 #define RXB_IDX_MAX 31
107 #define RXB_IDX_MIN 0
108
109 #define IGI_RSSI_MAX 110
110 #define PD_TH_MAX_RSSI 70
111 #define PD_TH_MIN_RSSI 8
112 #define CCKPD_TH_MIN_RSSI (-18)
113 #define PD_TH_BW160_CMP_VAL 9
114 #define PD_TH_BW80_CMP_VAL 6
115 #define PD_TH_BW40_CMP_VAL 3
116 #define PD_TH_BW20_CMP_VAL 0
117 #define PD_TH_CMP_VAL 3
118 #define PD_TH_SB_FLTR_CMP_VAL 7
119
120 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
121 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
122 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
123 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
124 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
125
126 #define EDCCA_MAX 249
127 #define EDCCA_TH_L2H_LB 66
128 #define EDCCA_TH_REF 3
129 #define EDCCA_HL_DIFF_NORMAL 8
130 #define RSSI_UNIT_CONVER 110
131 #define EDCCA_UNIT_CONVER 128
132 #define EDCCA_PWROFST_DEFAULT 18
133
134 enum rtw89_phy_c2h_ra_func {
135 RTW89_PHY_C2H_FUNC_STS_RPT,
136 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
137 RTW89_PHY_C2H_FUNC_TXSTS,
138 RTW89_PHY_C2H_FUNC_RA_MAX,
139 };
140
141 enum rtw89_phy_c2h_rfk_log_func {
142 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0,
143 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1,
144 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2,
145 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3,
146 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4,
147 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5,
148
149 RTW89_PHY_C2H_RFK_LOG_FUNC_NUM,
150 };
151
152 enum rtw89_phy_c2h_rfk_report_func {
153 RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0,
154 };
155
156 enum rtw89_phy_c2h_dm_func {
157 RTW89_PHY_C2H_DM_FUNC_FW_TEST,
158 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT,
159 RTW89_PHY_C2H_DM_FUNC_SIGB,
160 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY,
161 RTW89_PHY_C2H_DM_FUNC_MCC_DIG,
162 RTW89_PHY_C2H_DM_FUNC_NUM,
163 };
164
165 enum rtw89_phy_c2h_class {
166 RTW89_PHY_C2H_CLASS_RUA,
167 RTW89_PHY_C2H_CLASS_RA,
168 RTW89_PHY_C2H_CLASS_DM,
169 RTW89_PHY_C2H_RFK_LOG = 0x8,
170 RTW89_PHY_C2H_RFK_REPORT = 0x9,
171 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
172 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
173 RTW89_PHY_C2H_CLASS_MAX,
174 };
175
176 enum rtw89_env_monitor_result_level {
177 RTW89_PHY_ENV_MON_CCX_FAIL = 0,
178 RTW89_PHY_ENV_MON_NHM = BIT(0),
179 RTW89_PHY_ENV_MON_CLM = BIT(1),
180 RTW89_PHY_ENV_MON_FAHM = BIT(2),
181 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
182 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
183 };
184
185 #define CCX_US_BASE_RATIO 4
186 enum rtw89_ccx_unit {
187 RTW89_CCX_4_US = 0,
188 RTW89_CCX_8_US = 1,
189 RTW89_CCX_16_US = 2,
190 RTW89_CCX_32_US = 3
191 };
192
193 enum rtw89_phy_status_ie_type {
194 RTW89_PHYSTS_IE00_CMN_CCK = 0,
195 RTW89_PHYSTS_IE01_CMN_OFDM = 1,
196 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2,
197 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3,
198 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4,
199 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5,
200 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6,
201 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7,
202 RTW89_PHYSTS_IE08_FTR_CH = 8,
203 RTW89_PHYSTS_IE09_FTR_0 = 9,
204 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10,
205 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11,
206 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12,
207 RTW89_PHYSTS_IE13_DL_MU_DEF = 13,
208 RTW89_PHYSTS_IE14_TB_UL_CQI = 14,
209 RTW89_PHYSTS_IE15_TB_UL_DEF = 15,
210 RTW89_PHYSTS_IE16_RSVD16 = 16,
211 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17,
212 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18,
213 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19,
214 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20,
215 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21,
216 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22,
217 RTW89_PHYSTS_IE23_RSVD23 = 23,
218 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24,
219 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25,
220 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26,
221 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27,
222 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28,
223 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29,
224 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30,
225 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31,
226
227 /* keep last */
228 RTW89_PHYSTS_IE_NUM,
229 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
230 };
231
232 enum rtw89_phy_status_bitmap {
233 RTW89_TD_SEARCH_FAIL = 0,
234 RTW89_BRK_BY_TX_PKT = 1,
235 RTW89_CCA_SPOOF = 2,
236 RTW89_OFDM_BRK = 3,
237 RTW89_CCK_BRK = 4,
238 RTW89_DL_MU_SPOOFING = 5,
239 RTW89_HE_MU = 6,
240 RTW89_VHT_MU = 7,
241 RTW89_UL_TB_SPOOFING = 8,
242 RTW89_RSVD_9 = 9,
243 RTW89_TRIG_BASE_PPDU = 10,
244 RTW89_CCK_PKT = 11,
245 RTW89_LEGACY_OFDM_PKT = 12,
246 RTW89_HT_PKT = 13,
247 RTW89_VHT_PKT = 14,
248 RTW89_HE_PKT = 15,
249
250 RTW89_PHYSTS_BITMAP_NUM
251 };
252
253 enum rtw89_dig_gain_type {
254 RTW89_DIG_GAIN_LNA_G = 0,
255 RTW89_DIG_GAIN_TIA_G = 1,
256 RTW89_DIG_GAIN_LNA_A = 2,
257 RTW89_DIG_GAIN_TIA_A = 3,
258 RTW89_DIG_GAIN_MAX = 4
259 };
260
261 enum rtw89_dig_gain_lna_idx {
262 RTW89_DIG_GAIN_LNA_IDX1 = 1,
263 RTW89_DIG_GAIN_LNA_IDX2 = 2,
264 RTW89_DIG_GAIN_LNA_IDX3 = 3,
265 RTW89_DIG_GAIN_LNA_IDX4 = 4,
266 RTW89_DIG_GAIN_LNA_IDX5 = 5,
267 RTW89_DIG_GAIN_LNA_IDX6 = 6
268 };
269
270 enum rtw89_dig_gain_tia_idx {
271 RTW89_DIG_GAIN_TIA_IDX0 = 0,
272 RTW89_DIG_GAIN_TIA_IDX1 = 1
273 };
274
275 enum rtw89_tssi_bandedge_cfg {
276 RTW89_TSSI_BANDEDGE_FLAT,
277 RTW89_TSSI_BANDEDGE_LOW,
278 RTW89_TSSI_BANDEDGE_MID,
279 RTW89_TSSI_BANDEDGE_HIGH,
280
281 RTW89_TSSI_CFG_NUM,
282 };
283
284 enum rtw89_tssi_sbw_idx {
285 RTW89_TSSI_SBW20,
286 RTW89_TSSI_SBW40_0,
287 RTW89_TSSI_SBW40_1,
288 RTW89_TSSI_SBW80_0,
289 RTW89_TSSI_SBW80_1,
290 RTW89_TSSI_SBW80_2,
291 RTW89_TSSI_SBW80_3,
292 RTW89_TSSI_SBW160_0,
293 RTW89_TSSI_SBW160_1,
294 RTW89_TSSI_SBW160_2,
295 RTW89_TSSI_SBW160_3,
296 RTW89_TSSI_SBW160_4,
297 RTW89_TSSI_SBW160_5,
298 RTW89_TSSI_SBW160_6,
299 RTW89_TSSI_SBW160_7,
300
301 RTW89_TSSI_SBW_NUM,
302 };
303
304 struct rtw89_txpwr_byrate_cfg {
305 enum rtw89_band band;
306 enum rtw89_nss nss;
307 enum rtw89_rate_section rs;
308 u8 shf;
309 u8 len;
310 u32 data;
311 };
312
313 struct rtw89_txpwr_track_cfg {
314 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE];
315 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE];
316 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE];
317 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE];
318 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
319 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
320 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
321 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
322 const s8 *delta_swingidx_2gb_n;
323 const s8 *delta_swingidx_2gb_p;
324 const s8 *delta_swingidx_2ga_n;
325 const s8 *delta_swingidx_2ga_p;
326 const s8 *delta_swingidx_2g_cck_b_n;
327 const s8 *delta_swingidx_2g_cck_b_p;
328 const s8 *delta_swingidx_2g_cck_a_n;
329 const s8 *delta_swingidx_2g_cck_a_p;
330 };
331
332 struct rtw89_phy_dig_gain_cfg {
333 const struct rtw89_reg_def *table;
334 u8 size;
335 };
336
337 struct rtw89_phy_dig_gain_table {
338 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
339 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
340 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
341 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
342 };
343
344 struct rtw89_phy_tssi_dbw_table {
345 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
346 };
347
348 struct rtw89_phy_reg3_tbl {
349 const struct rtw89_reg3_def *reg3;
350 int size;
351 };
352
353 #define DECLARE_PHY_REG3_TBL(_name) \
354 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \
355 .reg3 = _name, \
356 .size = ARRAY_SIZE(_name), \
357 }
358
359 struct rtw89_nbi_reg_def {
360 struct rtw89_reg_def notch1_idx;
361 struct rtw89_reg_def notch1_frac_idx;
362 struct rtw89_reg_def notch1_en;
363 struct rtw89_reg_def notch2_idx;
364 struct rtw89_reg_def notch2_frac_idx;
365 struct rtw89_reg_def notch2_en;
366 };
367
368 struct rtw89_ccx_regs {
369 u32 setting_addr;
370 u32 edcca_opt_mask;
371 u32 measurement_trig_mask;
372 u32 trig_opt_mask;
373 u32 en_mask;
374 u32 ifs_cnt_addr;
375 u32 ifs_clm_period_mask;
376 u32 ifs_clm_cnt_unit_mask;
377 u32 ifs_clm_cnt_clear_mask;
378 u32 ifs_collect_en_mask;
379 u32 ifs_t1_addr;
380 u32 ifs_t1_th_h_mask;
381 u32 ifs_t1_en_mask;
382 u32 ifs_t1_th_l_mask;
383 u32 ifs_t2_addr;
384 u32 ifs_t2_th_h_mask;
385 u32 ifs_t2_en_mask;
386 u32 ifs_t2_th_l_mask;
387 u32 ifs_t3_addr;
388 u32 ifs_t3_th_h_mask;
389 u32 ifs_t3_en_mask;
390 u32 ifs_t3_th_l_mask;
391 u32 ifs_t4_addr;
392 u32 ifs_t4_th_h_mask;
393 u32 ifs_t4_en_mask;
394 u32 ifs_t4_th_l_mask;
395 u32 ifs_clm_tx_cnt_addr;
396 u32 ifs_clm_edcca_excl_cca_fa_mask;
397 u32 ifs_clm_tx_cnt_msk;
398 u32 ifs_clm_cca_addr;
399 u32 ifs_clm_ofdmcca_excl_fa_mask;
400 u32 ifs_clm_cckcca_excl_fa_mask;
401 u32 ifs_clm_fa_addr;
402 u32 ifs_clm_ofdm_fa_mask;
403 u32 ifs_clm_cck_fa_mask;
404 u32 ifs_his_addr;
405 u32 ifs_t4_his_mask;
406 u32 ifs_t3_his_mask;
407 u32 ifs_t2_his_mask;
408 u32 ifs_t1_his_mask;
409 u32 ifs_avg_l_addr;
410 u32 ifs_t2_avg_mask;
411 u32 ifs_t1_avg_mask;
412 u32 ifs_avg_h_addr;
413 u32 ifs_t4_avg_mask;
414 u32 ifs_t3_avg_mask;
415 u32 ifs_cca_l_addr;
416 u32 ifs_t2_cca_mask;
417 u32 ifs_t1_cca_mask;
418 u32 ifs_cca_h_addr;
419 u32 ifs_t4_cca_mask;
420 u32 ifs_t3_cca_mask;
421 u32 ifs_total_addr;
422 u32 ifs_cnt_done_mask;
423 u32 ifs_total_mask;
424 };
425
426 struct rtw89_physts_regs {
427 u32 setting_addr;
428 u32 dis_trigger_fail_mask;
429 u32 dis_trigger_brk_mask;
430 };
431
432 struct rtw89_cfo_regs {
433 u32 comp;
434 u32 weighting_mask;
435 u32 comp_seg0;
436 u32 valid_0_mask;
437 };
438
439 enum rtw89_bandwidth_section_num_ax {
440 RTW89_BW20_SEC_NUM_AX = 8,
441 RTW89_BW40_SEC_NUM_AX = 4,
442 RTW89_BW80_SEC_NUM_AX = 2,
443 };
444
445 enum rtw89_bandwidth_section_num_be {
446 RTW89_BW20_SEC_NUM_BE = 16,
447 RTW89_BW40_SEC_NUM_BE = 8,
448 RTW89_BW80_SEC_NUM_BE = 4,
449 RTW89_BW160_SEC_NUM_BE = 2,
450 };
451
452 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40
453
454 struct rtw89_txpwr_limit_ax {
455 s8 cck_20m[RTW89_BF_NUM];
456 s8 cck_40m[RTW89_BF_NUM];
457 s8 ofdm[RTW89_BF_NUM];
458 s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM];
459 s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM];
460 s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM];
461 s8 mcs_160m[RTW89_BF_NUM];
462 s8 mcs_40m_0p5[RTW89_BF_NUM];
463 s8 mcs_40m_2p5[RTW89_BF_NUM];
464 };
465
466 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76
467
468 struct rtw89_txpwr_limit_be {
469 s8 cck_20m[RTW89_BF_NUM];
470 s8 cck_40m[RTW89_BF_NUM];
471 s8 ofdm[RTW89_BF_NUM];
472 s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM];
473 s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM];
474 s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM];
475 s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM];
476 s8 mcs_320m[RTW89_BF_NUM];
477 s8 mcs_40m_0p5[RTW89_BF_NUM];
478 s8 mcs_40m_2p5[RTW89_BF_NUM];
479 s8 mcs_40m_4p5[RTW89_BF_NUM];
480 s8 mcs_40m_6p5[RTW89_BF_NUM];
481 };
482
483 #define RTW89_RU_SEC_NUM_AX 8
484
485 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24
486
487 struct rtw89_txpwr_limit_ru_ax {
488 s8 ru26[RTW89_RU_SEC_NUM_AX];
489 s8 ru52[RTW89_RU_SEC_NUM_AX];
490 s8 ru106[RTW89_RU_SEC_NUM_AX];
491 };
492
493 #define RTW89_RU_SEC_NUM_BE 16
494
495 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80
496
497 struct rtw89_txpwr_limit_ru_be {
498 s8 ru26[RTW89_RU_SEC_NUM_BE];
499 s8 ru52[RTW89_RU_SEC_NUM_BE];
500 s8 ru106[RTW89_RU_SEC_NUM_BE];
501 s8 ru52_26[RTW89_RU_SEC_NUM_BE];
502 s8 ru106_26[RTW89_RU_SEC_NUM_BE];
503 };
504
505 struct rtw89_phy_rfk_log_fmt {
506 const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM];
507 };
508
509 struct rtw89_phy_gen_def {
510 u32 cr_base;
511 const struct rtw89_ccx_regs *ccx;
512 const struct rtw89_physts_regs *physts;
513 const struct rtw89_cfo_regs *cfo;
514 u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
515 void (*config_bb_gain)(struct rtw89_dev *rtwdev,
516 const struct rtw89_reg2_def *reg,
517 enum rtw89_rf_path rf_path,
518 void *extra_data);
519 void (*preinit_rf_nctl)(struct rtw89_dev *rtwdev);
520 void (*bb_wrap_init)(struct rtw89_dev *rtwdev);
521 void (*ch_info_init)(struct rtw89_dev *rtwdev);
522
523 void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev,
524 const struct rtw89_chan *chan,
525 enum rtw89_phy_idx phy_idx);
526 void (*set_txpwr_offset)(struct rtw89_dev *rtwdev,
527 const struct rtw89_chan *chan,
528 enum rtw89_phy_idx phy_idx);
529 void (*set_txpwr_limit)(struct rtw89_dev *rtwdev,
530 const struct rtw89_chan *chan,
531 enum rtw89_phy_idx phy_idx);
532 void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev,
533 const struct rtw89_chan *chan,
534 enum rtw89_phy_idx phy_idx);
535 };
536
537 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax;
538 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be;
539
rtw89_phy_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)540 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
541 u32 addr, u8 data)
542 {
543 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
544
545 rtw89_write8(rtwdev, addr + phy->cr_base, data);
546 }
547
rtw89_phy_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)548 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
549 u32 addr, u16 data)
550 {
551 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
552
553 rtw89_write16(rtwdev, addr + phy->cr_base, data);
554 }
555
rtw89_phy_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)556 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
557 u32 addr, u32 data)
558 {
559 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
560
561 rtw89_write32(rtwdev, addr + phy->cr_base, data);
562 }
563
rtw89_phy_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits)564 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
565 u32 addr, u32 bits)
566 {
567 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
568
569 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits);
570 }
571
rtw89_phy_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits)572 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
573 u32 addr, u32 bits)
574 {
575 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
576
577 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits);
578 }
579
rtw89_phy_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)580 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
581 u32 addr, u32 mask, u32 data)
582 {
583 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
584
585 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data);
586 }
587
rtw89_phy_read8(struct rtw89_dev * rtwdev,u32 addr)588 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
589 {
590 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
591
592 return rtw89_read8(rtwdev, addr + phy->cr_base);
593 }
594
rtw89_phy_read16(struct rtw89_dev * rtwdev,u32 addr)595 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
596 {
597 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
598
599 return rtw89_read16(rtwdev, addr + phy->cr_base);
600 }
601
rtw89_phy_read32(struct rtw89_dev * rtwdev,u32 addr)602 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
603 {
604 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
605
606 return rtw89_read32(rtwdev, addr + phy->cr_base);
607 }
608
rtw89_phy_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)609 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
610 u32 addr, u32 mask)
611 {
612 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
613
614 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask);
615 }
616
rtw89_bbmcu_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data,enum rtw89_phy_idx phy_idx)617 static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev,
618 u32 addr, u32 data, enum rtw89_phy_idx phy_idx)
619 {
620 if (phy_idx && addr < 0x10000)
621 addr += 0x20000;
622
623 rtw89_write32(rtwdev, addr + RTW89_BBMCU_ADDR_OFFSET, data);
624 }
625
626 static inline
rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)627 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)
628 {
629 switch (subband) {
630 default:
631 case RTW89_CH_2G:
632 return RTW89_GAIN_OFFSET_2G_OFDM;
633 case RTW89_CH_5G_BAND_1:
634 return RTW89_GAIN_OFFSET_5G_LOW;
635 case RTW89_CH_5G_BAND_3:
636 return RTW89_GAIN_OFFSET_5G_MID;
637 case RTW89_CH_5G_BAND_4:
638 return RTW89_GAIN_OFFSET_5G_HIGH;
639 case RTW89_CH_6G_BAND_IDX0:
640 return RTW89_GAIN_OFFSET_6G_L0;
641 case RTW89_CH_6G_BAND_IDX1:
642 return RTW89_GAIN_OFFSET_6G_L1;
643 case RTW89_CH_6G_BAND_IDX2:
644 return RTW89_GAIN_OFFSET_6G_M0;
645 case RTW89_CH_6G_BAND_IDX3:
646 return RTW89_GAIN_OFFSET_6G_M1;
647 case RTW89_CH_6G_BAND_IDX4:
648 return RTW89_GAIN_OFFSET_6G_H0;
649 case RTW89_CH_6G_BAND_IDX5:
650 return RTW89_GAIN_OFFSET_6G_H1;
651 case RTW89_CH_6G_BAND_IDX6:
652 return RTW89_GAIN_OFFSET_6G_UH0;
653 case RTW89_CH_6G_BAND_IDX7:
654 return RTW89_GAIN_OFFSET_6G_UH1;
655 }
656 }
657
658 static inline
rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)659 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)
660 {
661 switch (subband) {
662 default:
663 case RTW89_CH_2G:
664 return RTW89_BB_GAIN_BAND_2G;
665 case RTW89_CH_5G_BAND_1:
666 return RTW89_BB_GAIN_BAND_5G_L;
667 case RTW89_CH_5G_BAND_3:
668 return RTW89_BB_GAIN_BAND_5G_M;
669 case RTW89_CH_5G_BAND_4:
670 return RTW89_BB_GAIN_BAND_5G_H;
671 case RTW89_CH_6G_BAND_IDX0:
672 case RTW89_CH_6G_BAND_IDX1:
673 return RTW89_BB_GAIN_BAND_6G_L;
674 case RTW89_CH_6G_BAND_IDX2:
675 case RTW89_CH_6G_BAND_IDX3:
676 return RTW89_BB_GAIN_BAND_6G_M;
677 case RTW89_CH_6G_BAND_IDX4:
678 case RTW89_CH_6G_BAND_IDX5:
679 return RTW89_BB_GAIN_BAND_6G_H;
680 case RTW89_CH_6G_BAND_IDX6:
681 case RTW89_CH_6G_BAND_IDX7:
682 return RTW89_BB_GAIN_BAND_6G_UH;
683 }
684 }
685
686 static inline
rtw89_subband_to_gain_band_be(enum rtw89_subband subband)687 enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband)
688 {
689 switch (subband) {
690 default:
691 case RTW89_CH_2G:
692 return RTW89_BB_GAIN_BAND_2G_BE;
693 case RTW89_CH_5G_BAND_1:
694 return RTW89_BB_GAIN_BAND_5G_L_BE;
695 case RTW89_CH_5G_BAND_3:
696 return RTW89_BB_GAIN_BAND_5G_M_BE;
697 case RTW89_CH_5G_BAND_4:
698 return RTW89_BB_GAIN_BAND_5G_H_BE;
699 case RTW89_CH_6G_BAND_IDX0:
700 return RTW89_BB_GAIN_BAND_6G_L0_BE;
701 case RTW89_CH_6G_BAND_IDX1:
702 return RTW89_BB_GAIN_BAND_6G_L1_BE;
703 case RTW89_CH_6G_BAND_IDX2:
704 return RTW89_BB_GAIN_BAND_6G_M0_BE;
705 case RTW89_CH_6G_BAND_IDX3:
706 return RTW89_BB_GAIN_BAND_6G_M1_BE;
707 case RTW89_CH_6G_BAND_IDX4:
708 return RTW89_BB_GAIN_BAND_6G_H0_BE;
709 case RTW89_CH_6G_BAND_IDX5:
710 return RTW89_BB_GAIN_BAND_6G_H1_BE;
711 case RTW89_CH_6G_BAND_IDX6:
712 return RTW89_BB_GAIN_BAND_6G_UH0_BE;
713 case RTW89_CH_6G_BAND_IDX7:
714 return RTW89_BB_GAIN_BAND_6G_UH1_BE;
715 }
716 }
717
718 struct rtw89_rfk_chan_desc {
719 /* desc is valid iff ch is non-zero */
720 u8 ch;
721
722 /* To avoid us from extending old chip code every time, each new
723 * field must be defined along with a bool flag in positivte way.
724 */
725 bool has_band;
726 u8 band;
727 bool has_bw;
728 u8 bw;
729 };
730
731 enum rtw89_rfk_flag {
732 RTW89_RFK_F_WRF = 0,
733 RTW89_RFK_F_WM = 1,
734 RTW89_RFK_F_WS = 2,
735 RTW89_RFK_F_WC = 3,
736 RTW89_RFK_F_DELAY = 4,
737 RTW89_RFK_F_NUM,
738 };
739
740 struct rtw89_rfk_tbl {
741 const struct rtw89_reg5_def *defs;
742 u32 size;
743 };
744
745 #define RTW89_DECLARE_RFK_TBL(_name) \
746 const struct rtw89_rfk_tbl _name ## _tbl = { \
747 .defs = _name, \
748 .size = ARRAY_SIZE(_name), \
749 }
750
751 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \
752 {.flag = RTW89_RFK_F_WRF, \
753 .path = _path, \
754 .addr = _addr, \
755 .mask = _mask, \
756 .data = _data,}
757
758 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \
759 {.flag = RTW89_RFK_F_WM, \
760 .addr = _addr, \
761 .mask = _mask, \
762 .data = _data,}
763
764 #define RTW89_DECL_RFK_WS(_addr, _mask) \
765 {.flag = RTW89_RFK_F_WS, \
766 .addr = _addr, \
767 .mask = _mask,}
768
769 #define RTW89_DECL_RFK_WC(_addr, _mask) \
770 {.flag = RTW89_RFK_F_WC, \
771 .addr = _addr, \
772 .mask = _mask,}
773
774 #define RTW89_DECL_RFK_DELAY(_data) \
775 {.flag = RTW89_RFK_F_DELAY, \
776 .data = _data,}
777
778 void
779 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl);
780
781 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \
782 do { \
783 typeof(dev) __dev = (dev); \
784 if (cond) \
785 rtw89_rfk_parser(__dev, (tbl_t)); \
786 else \
787 rtw89_rfk_parser(__dev, (tbl_f)); \
788 } while (0)
789
790 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
791 const struct rtw89_phy_reg3_tbl *tbl);
792 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
793 const struct rtw89_chan *chan,
794 enum rtw89_bandwidth dbw);
795 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
796 enum rtw89_bandwidth dbw);
797 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
798 u32 addr, u32 mask);
799 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
800 u32 addr, u32 mask);
801 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
802 u32 addr, u32 mask);
803 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
804 u32 addr, u32 mask, u32 data);
805 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
806 u32 addr, u32 mask, u32 data);
807 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
808 u32 addr, u32 mask, u32 data);
809 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
810 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
811 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
812 const struct rtw89_reg2_def *reg,
813 enum rtw89_rf_path rf_path,
814 void *extra_data);
815 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
816 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
817 u32 data, enum rtw89_phy_idx phy_idx);
818 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
819 enum rtw89_phy_idx phy_idx);
820 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
821 struct rtw89_txpwr_byrate *head,
822 const struct rtw89_rate_desc *desc);
823 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
824 const struct rtw89_rate_desc *rate_desc);
825 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
826 const struct rtw89_txpwr_table *tbl);
827 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
828 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
829 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
830 u8 ru, u8 ntx, u8 ch);
831
rtw89_phy_preinit_rf_nctl(struct rtw89_dev * rtwdev)832 static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev)
833 {
834 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
835
836 phy->preinit_rf_nctl(rtwdev);
837 }
838
rtw89_phy_bb_wrap_init(struct rtw89_dev * rtwdev)839 static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev)
840 {
841 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
842
843 if (phy->bb_wrap_init)
844 phy->bb_wrap_init(rtwdev);
845 }
846
rtw89_phy_ch_info_init(struct rtw89_dev * rtwdev)847 static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev)
848 {
849 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
850
851 if (phy->ch_info_init)
852 phy->ch_info_init(rtwdev);
853 }
854
855 static inline
rtw89_phy_set_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)856 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
857 const struct rtw89_chan *chan,
858 enum rtw89_phy_idx phy_idx)
859 {
860 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
861
862 phy->set_txpwr_byrate(rtwdev, chan, phy_idx);
863 }
864
865 static inline
rtw89_phy_set_txpwr_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)866 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
867 const struct rtw89_chan *chan,
868 enum rtw89_phy_idx phy_idx)
869 {
870 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
871
872 phy->set_txpwr_offset(rtwdev, chan, phy_idx);
873 }
874
875 static inline
rtw89_phy_set_txpwr_limit(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)876 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
877 const struct rtw89_chan *chan,
878 enum rtw89_phy_idx phy_idx)
879 {
880 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
881
882 phy->set_txpwr_limit(rtwdev, chan, phy_idx);
883 }
884
885 static inline
rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)886 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
887 const struct rtw89_chan *chan,
888 enum rtw89_phy_idx phy_idx)
889 {
890 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
891
892 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx);
893 }
894
895 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
896 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
897 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
898 u32 changed);
899 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
900 struct ieee80211_vif *vif,
901 const struct cfg80211_bitrate_mask *mask);
902 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func);
903 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
904 u32 len, u8 class, u8 func);
905 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
906 enum rtw89_phy_idx phy_idx,
907 unsigned int ms);
908 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
909 enum rtw89_phy_idx phy_idx,
910 const struct rtw89_chan *chan,
911 enum rtw89_tssi_mode tssi_mode,
912 unsigned int ms);
913 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
914 enum rtw89_phy_idx phy_idx,
915 const struct rtw89_chan *chan,
916 unsigned int ms);
917 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
918 enum rtw89_phy_idx phy_idx,
919 const struct rtw89_chan *chan,
920 unsigned int ms);
921 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
922 enum rtw89_phy_idx phy_idx,
923 const struct rtw89_chan *chan,
924 unsigned int ms);
925 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
926 enum rtw89_phy_idx phy_idx,
927 const struct rtw89_chan *chan,
928 unsigned int ms);
929 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
930 enum rtw89_phy_idx phy_idx,
931 const struct rtw89_chan *chan,
932 unsigned int ms);
933 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
934 enum rtw89_phy_idx phy,
935 const struct rtw89_chan *chan,
936 struct rtw89_h2c_rf_tssi *h2c);
937 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
938 enum rtw89_phy_idx phy,
939 const struct rtw89_chan *chan,
940 struct rtw89_h2c_rf_tssi *h2c);
941 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
942 void rtw89_phy_cfo_track_work(struct work_struct *work);
943 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
944 struct rtw89_rx_phy_ppdu *phy_ppdu);
945 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
946 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
947 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
948 u32 val);
949 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev);
950 void rtw89_phy_dig(struct rtw89_dev *rtwdev);
951 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev);
952 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
953 struct rtw89_rx_phy_ppdu *phy_ppdu);
954 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev);
955 void rtw89_phy_antdiv_work(struct work_struct *work);
956 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
957 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
958 enum rtw89_mac_idx mac_idx,
959 enum rtw89_tssi_bandedge_cfg bandedge_cfg);
960 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
961 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
962 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band);
963 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
964 u8 *ch, enum nl80211_band *band);
965 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan);
966 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev);
967 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev);
968 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
969 enum rtw89_phy_idx phy_idx);
970 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
971 enum rtw89_phy_idx phy_idx);
972 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
973 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
974 const struct rtw89_chan *target_chan);
975
976 #endif
977