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/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,wcd937x-sdw.yaml31 WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
32 WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2
33 WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
34 WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
49 WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R)
50 WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH)
51 WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R)
52 WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO)
53 WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
/linux/Documentation/PCI/
H A Dpciebus-howto.rst5 The PCI Express Port Bus Driver Guide HOWTO
16 register/unregister with the PCI Express Port Bus Driver.
19 What is the PCI Express Port Bus Driver
23 are two types of PCI Express Port: the Root Port and the Switch
24 Port. The Root Port originates a PCI Express link from a PCI Express
25 Root Complex and the Switch Port connects PCI Express links to
28 switch's Upstream Port. The switch's Downstream Port is bridging from
40 Why use the PCI Express Port Bus Driver?
63 a PCI-PCI Bridge Port device.
69 Port devices.
[all …]
/linux/drivers/usb/serial/
H A Dio_ionsp.h124 #define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78))… argument
125 #define IOSP_BUILD_DATA_HDR2(Port, Len) ((__u8) (Len)) argument
131 #define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3))… argument
193 #define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \ argument
195 (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), \
203 #define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \ argument
205 (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD); \
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi92 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
93 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
94 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
95 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
96 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
97 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
98 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
99 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
101 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
102 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
[all …]
H A Darmada-xp-mv78260.dtsi74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
77 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
78 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
[all …]
H A Darmada-xp-mv78230.dtsi65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
74 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
75 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
77 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
[all …]
H A Darmada-385.dtsi52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
56 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
57 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
58 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
59 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
H A Darmada-380.dtsi53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
55 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
57 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
58 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dmvebu-pci.txt113 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
114 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
115 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
116 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
117 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
118 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
119 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
120 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
122 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
123 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
[all …]
/linux/drivers/usb/typec/tcpm/
H A DKconfig4 tristate "USB Type-C Port Controller Manager"
9 The Type-C Port Controller Manager provides a USB PD and USB Type-C
10 state machine for use with Type-C Port Controllers.
15 tristate "Type-C Port Controller Interface driver"
19 Type-C Port Controller driver for TCPCI-compliant controller.
27 Type-C Port Controller Manager to provide USB PD and USB
35 USB Type-C. It works with Type-C Port Controller Manager
43 USB Type-C. It works with Type-C Port Controller Manager
53 with Type-C Port Controller Manager.
63 Type-C Port Controller Manager to provide USB PD and USB
[all …]
/linux/Documentation/driver-api/tty/
H A Dtty_port.rst4 TTY Port
15 The reference and details are contained in the `TTY Port Reference`_ and `TTY
16 Port Operations Reference`_ sections at the bottom.
18 TTY Port Functions
58 TTY Port Reference
66 TTY Port Operations Reference
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8650-qrd.dts1091 * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
1092 * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
1094 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
1095 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
1096 * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
1114 * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
1115 * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
1117 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
1118 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
1119 * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
[all …]
H A Dsm8650-hdk.dts1139 * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
1140 * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
1142 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
1143 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
1144 * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
1162 * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
1163 * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
1165 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
1166 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
1167 * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
[all …]
H A Dsm8650-mtp.dts756 * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
757 * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
758 * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
759 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
760 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
761 * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
779 * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
780 * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
782 * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
783 * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
[all …]
/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dts208 reg = <0x3>; /* Port */
215 reg = <0x4>; /* Port */
220 reg = <0x5>; /* Port */
225 reg = <0x6>; /* Port */
230 reg = <0x7>; /* Port */
235 reg = <0x8>; /* Port */
240 reg = <0x9>; /* Port */
245 reg = <0xa>; /* Port */
250 reg = <0xb>; /* Port */
255 reg = <0xc>; /* Port */
[all …]
H A Docteon_68xx.dts269 reg = <0x0>; /* Port */
275 reg = <0x1>; /* Port */
281 reg = <0x2>; /* Port */
287 reg = <0x3>; /* Port */
301 reg = <0x0>; /* Port */
307 reg = <0x1>; /* Port */
313 reg = <0x2>; /* Port */
319 reg = <0x3>; /* Port */
333 reg = <0x0>; /* Port */
339 reg = <0x1>; /* Port */
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Donnn,nb7vpq904m.yaml66 - Port A to RX2 lane
67 - Port B to TX2 lane
68 - Port C to TX1 lane
69 - Port D to RX1 lane
77 - Port A to RX1 lane
78 - Port B to TX1 lane
79 - Port C to TX2 lane
80 - Port D to RX2 lane
H A Dti,hd3ss3220.yaml7 title: TI HD3SS3220 TypeC DRP Port Controller
15 HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a
16 Dual Role Port (DRP) making it ideal for any application.
/linux/Documentation/arch/s390/
H A Dqeth.rst5 OSA and HiperSockets Bridge Port Support
12 a primary or a secondary Bridge Port. For more information, see
15 When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state
16 of some configured Bridge Port device on the channel changes, a udev
21 indicates that the Bridge Port device changed
30 When run on HiperSockets Bridge Capable Port hardware with host address
39 deregistered on the Bridge Port HiperSockets channel, or address
/linux/drivers/pci/pcie/
H A DKconfig3 # PCI Express Port Bus Configuration
6 bool "PCI Express Port Bus support"
9 This enables PCI Express Port Bus support. Users can then enable
11 Management Events, and Downstream Port Containment.
33 This enables PCI Express Root Port Advanced Error Reporting
35 Port will be handled by PCI Express AER driver.
42 This enables PCI Express Root Port Advanced Error Reporting
131 bool "PCI Express Downstream Port Containment support"
134 This enables PCI Express Downstream Port Containment (DPC)
154 in the Downstream Port Containment Related Enhancements ECN to
/linux/Documentation/gpu/dp-mst/
H A Dtopology-figure-1.dot48 port1 [label="Port #1";shape=oval];
49 port2 [label="Port #2";shape=oval];
50 port3 [label="Port #3";shape=oval];
51 port4 [label="Port #4";shape=oval];
H A Dtopology-figure-2.dot47 port1 [label="Port #1"];
48 port2 [label="Port #2"];
49 port3 [label="Port #3"];
50 port4 [label="Port #4";style=filled;fillcolor=grey];
H A Dtopology-figure-3.dot50 port1 [label="Port #1"];
51 port2 [label="Port #2";penwidth=5];
52 port3 [label="Port #3";penwidth=3];
53 port4 [label="Port #4";style=filled;fillcolor=grey];
/linux/Documentation/devicetree/bindings/net/
H A Dcavium-pip.txt62 reg = <0x0>; /* Port */
68 reg = <0x1>; /* Port */
74 reg = <0x2>; /* Port */
80 reg = <0x3>; /* Port */
94 reg = <0x0>; /* Port */

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