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Searched refs:REF_CLK (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/net/
H A Dnxp,tja11xx.yaml52 The REF_CLK is provided for both transmitted and received data
56 connected to pin REF_CLK. A third option is to connect a 25MHz
57 clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
59 If present, indicates that the REF_CLK will be configured as
61 If not present, the REF_CLK will be configured as interface
/linux/Documentation/devicetree/bindings/clock/
H A Dcirrus,cs2000-cp.yaml25 Common clock binding for CLK_IN, XTI/REF_CLK
61 output signal directly from the REF_CLK input.
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-iot2050-usb3.dtsi17 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
H A Dk3-am6548-iot2050-advanced-m2-bkey-usb3.dtso37 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
H A Dk3-am654-pcie-usb3.dtso44 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
H A Dk3-am65-main.dtsi533 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
573 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
/linux/include/dt-bindings/clock/
H A Dxlnx-versal-clk.h115 #define REF_CLK 106 macro
/linux/drivers/clk/
H A Dclk-cs2000-cp.c75 #define REF_CLK 1 macro
427 return priv->dynamic_mode ? CLK_IN : REF_CLK; in cs2000_get_parent()
506 parent_names[REF_CLK] = __clk_get_name(priv->ref_clk); in cs2000_clk_register()
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dchipone,icn6211.yaml33 Optional external clock connected to REF_CLK input.
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-sielaff.dts154 * REF_CLK from the PHY is fed back into the i.MX6 and the GPR
/linux/drivers/pinctrl/
H A Dpinctrl-ocelot.c740 SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M);
741 SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M);
742 SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
743 SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);