1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50
51 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
52 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
53 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
54 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
55 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
56 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
57 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
58 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
59 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
60 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
61 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
62 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
63 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
64 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
65 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
66 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
67 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
68 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
69 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
70 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
71 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
72 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
73 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
74 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
75 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
76
77 struct rtw89_h2creg_hdr {
78 u32 w0;
79 };
80
81 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
82 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
83
84 struct rtw89_h2creg_sch_tx_en {
85 u32 w0;
86 u32 w1;
87 } __packed;
88
89 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
90 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
91 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
92
93 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
94
95 #define RTW89_H2CREG_MAX 4
96 #define RTW89_C2HREG_MAX 4
97 #define RTW89_C2HREG_HDR_LEN 2
98 #define RTW89_H2CREG_HDR_LEN 2
99 #define RTW89_C2H_TIMEOUT 1000000
100 struct rtw89_mac_c2h_info {
101 u8 id;
102 u8 content_len;
103 union {
104 u32 c2hreg[RTW89_C2HREG_MAX];
105 struct rtw89_c2hreg_hdr hdr;
106 struct rtw89_c2hreg_phycap phycap;
107 } u;
108 };
109
110 struct rtw89_mac_h2c_info {
111 u8 id;
112 u8 content_len;
113 union {
114 u32 h2creg[RTW89_H2CREG_MAX];
115 struct rtw89_h2creg_hdr hdr;
116 struct rtw89_h2creg_sch_tx_en sch_tx_en;
117 } u;
118 };
119
120 enum rtw89_mac_h2c_type {
121 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
122 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
123 RTW89_FWCMD_H2CREG_FUNC_FWERR,
124 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
125 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
126 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
127 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
128 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
129 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
130 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
131 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
132 };
133
134 enum rtw89_mac_c2h_type {
135 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
136 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
137 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
138 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
139 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
140 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
141 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
142 };
143
144 enum rtw89_fw_c2h_category {
145 RTW89_C2H_CAT_TEST,
146 RTW89_C2H_CAT_MAC,
147 RTW89_C2H_CAT_OUTSRC,
148 };
149
150 enum rtw89_fw_log_level {
151 RTW89_FW_LOG_LEVEL_OFF,
152 RTW89_FW_LOG_LEVEL_CRT,
153 RTW89_FW_LOG_LEVEL_SER,
154 RTW89_FW_LOG_LEVEL_WARN,
155 RTW89_FW_LOG_LEVEL_LOUD,
156 RTW89_FW_LOG_LEVEL_TR,
157 };
158
159 enum rtw89_fw_log_path {
160 RTW89_FW_LOG_LEVEL_UART,
161 RTW89_FW_LOG_LEVEL_C2H,
162 RTW89_FW_LOG_LEVEL_SNI,
163 };
164
165 enum rtw89_fw_log_comp {
166 RTW89_FW_LOG_COMP_VER,
167 RTW89_FW_LOG_COMP_INIT,
168 RTW89_FW_LOG_COMP_TASK,
169 RTW89_FW_LOG_COMP_CNS,
170 RTW89_FW_LOG_COMP_H2C,
171 RTW89_FW_LOG_COMP_C2H,
172 RTW89_FW_LOG_COMP_TX,
173 RTW89_FW_LOG_COMP_RX,
174 RTW89_FW_LOG_COMP_IPSEC,
175 RTW89_FW_LOG_COMP_TIMER,
176 RTW89_FW_LOG_COMP_DBGPKT,
177 RTW89_FW_LOG_COMP_PS,
178 RTW89_FW_LOG_COMP_ERROR,
179 RTW89_FW_LOG_COMP_WOWLAN,
180 RTW89_FW_LOG_COMP_SECURE_BOOT,
181 RTW89_FW_LOG_COMP_BTC,
182 RTW89_FW_LOG_COMP_BB,
183 RTW89_FW_LOG_COMP_TWT,
184 RTW89_FW_LOG_COMP_RF,
185 RTW89_FW_LOG_COMP_MCC = 20,
186 RTW89_FW_LOG_COMP_SCAN = 28,
187 };
188
189 enum rtw89_pkt_offload_op {
190 RTW89_PKT_OFLD_OP_ADD,
191 RTW89_PKT_OFLD_OP_DEL,
192 RTW89_PKT_OFLD_OP_READ,
193
194 NUM_OF_RTW89_PKT_OFFLOAD_OP,
195 };
196
197 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
198 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
199
200 enum rtw89_scanofld_notify_reason {
201 RTW89_SCAN_DWELL_NOTIFY,
202 RTW89_SCAN_PRE_TX_NOTIFY,
203 RTW89_SCAN_POST_TX_NOTIFY,
204 RTW89_SCAN_ENTER_CH_NOTIFY,
205 RTW89_SCAN_LEAVE_CH_NOTIFY,
206 RTW89_SCAN_END_SCAN_NOTIFY,
207 RTW89_SCAN_REPORT_NOTIFY,
208 RTW89_SCAN_CHKPT_NOTIFY,
209 RTW89_SCAN_ENTER_OP_NOTIFY,
210 RTW89_SCAN_LEAVE_OP_NOTIFY,
211 };
212
213 enum rtw89_scanofld_status {
214 RTW89_SCAN_STATUS_NOTIFY,
215 RTW89_SCAN_STATUS_SUCCESS,
216 RTW89_SCAN_STATUS_FAIL,
217 };
218
219 enum rtw89_chan_type {
220 RTW89_CHAN_OPERATE = 0,
221 RTW89_CHAN_ACTIVE,
222 RTW89_CHAN_DFS,
223 };
224
225 enum rtw89_p2pps_action {
226 RTW89_P2P_ACT_INIT = 0,
227 RTW89_P2P_ACT_UPDATE = 1,
228 RTW89_P2P_ACT_REMOVE = 2,
229 RTW89_P2P_ACT_TERMINATE = 3,
230 };
231
232 #define RTW89_DEFAULT_CQM_HYST 4
233 #define RTW89_DEFAULT_CQM_THOLD -70
234
235 enum rtw89_bcn_fltr_offload_mode {
236 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
237 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
238 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
239 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
240
241 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
242 };
243
244 enum rtw89_bcn_fltr_type {
245 RTW89_BCN_FLTR_BEACON_LOSS,
246 RTW89_BCN_FLTR_RSSI,
247 RTW89_BCN_FLTR_NOTIFY,
248 };
249
250 enum rtw89_bcn_fltr_rssi_event {
251 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
252 RTW89_BCN_FLTR_RSSI_HIGH,
253 RTW89_BCN_FLTR_RSSI_LOW,
254 };
255
256 #define FWDL_SECTION_MAX_NUM 10
257 #define FWDL_SECTION_CHKSUM_LEN 8
258 #define FWDL_SECTION_PER_PKT_LEN 2020
259
260 struct rtw89_fw_hdr_section_info {
261 u8 redl;
262 const u8 *addr;
263 u32 len;
264 u32 dladdr;
265 u32 mssc;
266 u8 type;
267 bool ignore;
268 const u8 *key_addr;
269 u32 key_len;
270 u32 key_idx;
271 };
272
273 struct rtw89_fw_bin_info {
274 u8 section_num;
275 u32 hdr_len;
276 bool dynamic_hdr_en;
277 u32 dynamic_hdr_len;
278 bool dsp_checksum;
279 bool secure_section_exist;
280 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
281 };
282
283 struct rtw89_fw_macid_pause_grp {
284 __le32 pause_grp[4];
285 __le32 mask_grp[4];
286 } __packed;
287
288 struct rtw89_fw_macid_pause_sleep_grp {
289 struct {
290 __le32 pause_grp[4];
291 __le32 pause_mask_grp[4];
292 __le32 sleep_grp[4];
293 __le32 sleep_mask_grp[4];
294 } __packed n[4];
295 } __packed;
296
297 #define RTW89_H2C_MAX_SIZE 2048
298 #define RTW89_CHANNEL_TIME 45
299 #define RTW89_CHANNEL_TIME_6G 20
300 #define RTW89_DFS_CHAN_TIME 105
301 #define RTW89_OFF_CHAN_TIME 100
302 #define RTW89_DWELL_TIME 20
303 #define RTW89_DWELL_TIME_6G 10
304 #define RTW89_SCAN_WIDTH 0
305 #define RTW89_SCANOFLD_MAX_SSID 8
306 #define RTW89_SCANOFLD_MAX_IE_LEN 512
307 #define RTW89_SCANOFLD_PKT_NONE 0xFF
308 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
309 #define RTW89_CHAN_INVALID 0xFF
310 #define RTW89_MAC_CHINFO_SIZE 28
311 #define RTW89_SCAN_LIST_GUARD 4
312 #define RTW89_SCAN_LIST_LIMIT \
313 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
314
315 #define RTW89_BCN_LOSS_CNT 10
316
317 struct rtw89_mac_chinfo {
318 u8 period;
319 u8 dwell_time;
320 u8 central_ch;
321 u8 pri_ch;
322 u8 bw:3;
323 u8 notify_action:5;
324 u8 num_pkt:4;
325 u8 tx_pkt:1;
326 u8 pause_data:1;
327 u8 ch_band:2;
328 u8 probe_id;
329 u8 dfs_ch:1;
330 u8 tx_null:1;
331 u8 rand_seq_num:1;
332 u8 cfg_tx_pwr:1;
333 u8 rsvd0: 4;
334 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
335 u16 tx_pwr_idx;
336 u8 rsvd1;
337 struct list_head list;
338 bool is_psc;
339 };
340
341 struct rtw89_mac_chinfo_be {
342 u8 period;
343 u8 dwell_time;
344 u8 central_ch;
345 u8 pri_ch;
346 u8 bw:3;
347 u8 ch_band:2;
348 u8 dfs_ch:1;
349 u8 pause_data:1;
350 u8 tx_null:1;
351 u8 rand_seq_num:1;
352 u8 notify_action:5;
353 u8 probe_id;
354 u8 leave_crit;
355 u8 chkpt_timer;
356 u8 leave_time;
357 u8 leave_th;
358 u16 tx_pkt_ctrl;
359 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
360 u8 sw_def;
361 u16 fw_probe0_ssids;
362 u16 fw_probe0_shortssids;
363 u16 fw_probe0_bssids;
364
365 struct list_head list;
366 bool is_psc;
367 };
368
369 struct rtw89_pktofld_info {
370 struct list_head list;
371 u8 id;
372 bool wildcard_6ghz;
373
374 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
375 u8 ssid[IEEE80211_MAX_SSID_LEN];
376 u8 ssid_len;
377 u8 bssid[ETH_ALEN];
378 u16 channel_6ghz;
379 bool cancel;
380 };
381
382 struct rtw89_h2c_ra {
383 __le32 w0;
384 __le32 w1;
385 __le32 w2;
386 __le32 w3;
387 } __packed;
388
389 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
390 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
391 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
392 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
393 #define RTW89_H2C_RA_W0_DCM BIT(16)
394 #define RTW89_H2C_RA_W0_ER BIT(17)
395 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
396 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
397 #define RTW89_H2C_RA_W0_SGI BIT(21)
398 #define RTW89_H2C_RA_W0_LDPC BIT(22)
399 #define RTW89_H2C_RA_W0_STBC BIT(23)
400 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
401 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
402 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
403 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
404 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
405 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
406 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
407 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
408 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
409 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
410 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
411 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
412 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
413 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
414 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
415 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
416 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
417
418 struct rtw89_h2c_ra_v1 {
419 struct rtw89_h2c_ra v0;
420 __le32 w4;
421 __le32 w5;
422 } __packed;
423
424 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
425 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
426 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
427 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
428
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)429 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
430 {
431 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
432 }
433
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)434 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
435 {
436 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
437 }
438
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)439 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
440 {
441 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
442 }
443
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)444 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
445 {
446 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
447 }
448
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)449 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
450 {
451 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
452 }
453
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)454 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
455 {
456 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
457 }
458
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)459 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
460 {
461 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
462 }
463
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)464 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
465 {
466 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
467 }
468
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)469 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
470 {
471 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
472 }
473
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)474 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
475 {
476 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
477 }
478
RTW89_SET_EDCA_SEL(void * cmd,u32 val)479 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
480 {
481 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
482 }
483
RTW89_SET_EDCA_BAND(void * cmd,u32 val)484 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
485 {
486 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
487 }
488
RTW89_SET_EDCA_WMM(void * cmd,u32 val)489 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
490 {
491 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
492 }
493
RTW89_SET_EDCA_AC(void * cmd,u32 val)494 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
495 {
496 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
497 }
498
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)499 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
500 {
501 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
502 }
503 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
504 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
505 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
506 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
507
508 #define FWDL_SECURITY_SECTION_TYPE 9
509 #define FWDL_SECURITY_SIGLEN 512
510 #define FWDL_SECURITY_CHKSUM_LEN 8
511
512 struct rtw89_fw_dynhdr_sec {
513 __le32 w0;
514 u8 content[];
515 } __packed;
516
517 struct rtw89_fw_dynhdr_hdr {
518 __le32 hdr_len;
519 __le32 setcion_count;
520 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
521 } __packed;
522
523 struct rtw89_fw_hdr_section {
524 __le32 w0;
525 __le32 w1;
526 __le32 w2;
527 __le32 w3;
528 } __packed;
529
530 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
531 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
532 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
533 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
534 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
535 #define FWSECTION_HDR_W1_REDL BIT(29)
536 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
537
538 struct rtw89_fw_hdr {
539 __le32 w0;
540 __le32 w1;
541 __le32 w2;
542 __le32 w3;
543 __le32 w4;
544 __le32 w5;
545 __le32 w6;
546 __le32 w7;
547 struct rtw89_fw_hdr_section sections[];
548 /* struct rtw89_fw_dynhdr_hdr (optional) */
549 } __packed;
550
551 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
552 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
553 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
554 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
555 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
556 #define FW_HDR_W3_LEN GENMASK(23, 16)
557 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
558 #define FW_HDR_W4_MONTH GENMASK(7, 0)
559 #define FW_HDR_W4_DATE GENMASK(15, 8)
560 #define FW_HDR_W4_HOUR GENMASK(23, 16)
561 #define FW_HDR_W4_MIN GENMASK(31, 24)
562 #define FW_HDR_W5_YEAR GENMASK(31, 0)
563 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
564 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
565 #define FW_HDR_W7_DYN_HDR BIT(16)
566 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
567
568 struct rtw89_fw_hdr_section_v1 {
569 __le32 w0;
570 __le32 w1;
571 __le32 w2;
572 __le32 w3;
573 } __packed;
574
575 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
576 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
577 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
578 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
579 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
580 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
581 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
582 #define FORMATTED_MSSC 0xFF
583 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
584
585 struct rtw89_fw_hdr_v1 {
586 __le32 w0;
587 __le32 w1;
588 __le32 w2;
589 __le32 w3;
590 __le32 w4;
591 __le32 w5;
592 __le32 w6;
593 __le32 w7;
594 __le32 w8;
595 __le32 w9;
596 __le32 w10;
597 __le32 w11;
598 struct rtw89_fw_hdr_section_v1 sections[];
599 } __packed;
600
601 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
602 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
603 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
604 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
605 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
606 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
607 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
608 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
609 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
610 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
611 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
612 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
613 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
614 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
615 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
616 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
617 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
618
619 enum rtw89_fw_mss_pool_rmp_tbl_type {
620 MSS_POOL_RMP_TBL_BITMASK = 0x0,
621 MSS_POOL_RMP_TBL_RECORD = 0x1,
622 };
623
624 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
625
626 struct rtw89_fw_mss_pool_hdr {
627 u8 signature[8]; /* equal to mss_signature[] */
628 __le32 rmp_tbl_offset;
629 __le32 key_raw_offset;
630 u8 defen;
631 u8 rsvd[3];
632 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
633 u8 mssdev_max;
634 __le16 keypair_num;
635 __le16 msscust_max;
636 __le16 msskey_num_max;
637 __le32 rsvd3;
638 u8 rmp_tbl[];
639 } __packed;
640
641 union rtw89_fw_section_mssc_content {
642 struct {
643 u8 pad[58];
644 __le32 v;
645 } __packed sb_sel_ver;
646 struct {
647 u8 pad[60];
648 __le16 v;
649 } __packed key_sign_len;
650 } __packed;
651
SET_CTRL_INFO_MACID(void * table,u32 val)652 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
653 {
654 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
655 }
656
SET_CTRL_INFO_OPERATION(void * table,u32 val)657 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
658 {
659 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
660 }
661 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)662 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
663 {
664 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
665 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
666 GENMASK(8, 0));
667 }
668 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)669 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
670 {
671 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
672 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
673 BIT(9));
674 }
675 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)676 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
677 {
678 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
679 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
680 GENMASK(11, 10));
681 }
682 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)683 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
684 {
685 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
686 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
687 GENMASK(14, 12));
688 }
689 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)690 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
691 {
692 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
693 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
694 BIT(15));
695 }
696 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)697 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
698 {
699 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
700 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
701 GENMASK(19, 16));
702 }
703 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)704 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
705 {
706 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
707 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
708 BIT(20));
709 }
710 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)711 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
712 {
713 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
714 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
715 BIT(21));
716 }
717 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)718 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
719 {
720 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
721 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
722 BIT(22));
723 }
724 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)725 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
726 {
727 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
728 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
729 BIT(23));
730 }
731 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)732 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
733 {
734 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
735 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
736 BIT(25));
737 }
738 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)739 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
740 {
741 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
742 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
743 BIT(26));
744 }
745 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)746 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
747 {
748 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
749 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
750 BIT(27));
751 }
752 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)753 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
754 {
755 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
756 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
757 GENMASK(31, 28));
758 }
759 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)760 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
761 {
762 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
763 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
764 GENMASK(8, 0));
765 }
766 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)767 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
768 {
769 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
770 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
771 BIT(9));
772 }
773 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)774 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
775 {
776 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
777 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
778 BIT(10));
779 }
780 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)781 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
782 {
783 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
784 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
785 BIT(11));
786 }
787 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)788 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
789 {
790 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
791 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
792 GENMASK(15, 12));
793 }
794 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)795 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
796 {
797 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
798 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
799 GENMASK(24, 16));
800 }
801 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)802 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
803 {
804 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
805 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
806 BIT(27));
807 }
808 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)809 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
810 {
811 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
812 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
813 GENMASK(31, 28));
814 }
815 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)816 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
817 {
818 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
819 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
820 GENMASK(5, 0));
821 }
822 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)823 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
824 {
825 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
826 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
827 BIT(6));
828 }
829 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)830 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
831 {
832 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
833 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
834 BIT(7));
835 }
836 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)837 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
838 {
839 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
840 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
841 BIT(8));
842 }
843 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)844 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
845 {
846 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
847 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
848 BIT(9));
849 }
850 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)851 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
852 {
853 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
854 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
855 GENMASK(11, 10));
856 }
857 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)858 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
859 {
860 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
861 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
862 BIT(12));
863 }
864 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)865 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
866 {
867 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
868 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
869 GENMASK(14, 13));
870 }
871 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)872 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
873 {
874 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
875 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
876 GENMASK(26, 16));
877 }
878 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)879 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
880 {
881 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
882 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
883 BIT(27));
884 }
885 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)886 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
887 {
888 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
889 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
890 GENMASK(31, 28));
891 }
892 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)893 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
894 {
895 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
896 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
897 GENMASK(7, 0));
898 }
899 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)900 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
901 {
902 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
903 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
904 GENMASK(9, 8));
905 }
906 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)907 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
908 {
909 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
910 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
911 GENMASK(18, 16));
912 }
913 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)914 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
915 {
916 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
917 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
918 GENMASK(21, 19));
919 }
920 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)921 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
922 {
923 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
924 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
925 GENMASK(24, 22));
926 }
927 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)928 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
929 {
930 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
931 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
932 GENMASK(27, 25));
933 }
934 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)935 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
936 {
937 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
938 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
939 GENMASK(31, 28));
940 }
941 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)942 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
943 {
944 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
945 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
946 GENMASK(2, 0));
947 }
948 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)949 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
950 {
951 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
952 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
953 BIT(3));
954 }
955 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)956 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
957 {
958 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
959 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
960 GENMASK(7, 4));
961 }
962 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)963 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
964 {
965 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
966 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
967 BIT(8));
968 }
969 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)970 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
971 {
972 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
973 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
974 GENMASK(11, 9));
975 }
976 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)977 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
978 {
979 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
980 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
981 BIT(12));
982 }
983 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)984 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
985 {
986 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
987 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
988 BIT(13));
989 }
990 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)991 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
992 {
993 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
994 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
995 BIT(14));
996 }
997 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)998 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
999 {
1000 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1001 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1002 BIT(15));
1003 }
1004 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)1005 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1006 {
1007 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1008 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1009 BIT(16));
1010 }
1011 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)1012 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1013 {
1014 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1015 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1016 BIT(17));
1017 }
1018 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)1019 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1020 {
1021 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1022 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1023 BIT(18));
1024 }
1025 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)1026 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1027 {
1028 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1029 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1030 BIT(19));
1031 }
1032 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)1033 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1034 {
1035 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1036 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1037 BIT(20));
1038 }
1039 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)1040 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1041 {
1042 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1043 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1044 BIT(21));
1045 }
1046 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)1047 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1048 {
1049 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1050 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1051 BIT(27));
1052 }
1053 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)1054 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1055 {
1056 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1057 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1058 GENMASK(31, 28));
1059 }
1060 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)1061 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1062 {
1063 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1064 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1065 GENMASK(8, 0));
1066 }
1067 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)1068 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1069 {
1070 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1071 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1072 BIT(12));
1073 }
1074 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)1075 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1076 {
1077 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1078 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1079 BIT(13));
1080 }
1081 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)1082 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1083 {
1084 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1085 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1086 GENMASK(19, 16));
1087 }
1088 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)1089 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1090 {
1091 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1092 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1093 GENMASK(21, 20));
1094 }
1095 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)1096 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1097 {
1098 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1099 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1100 GENMASK(23, 22));
1101 }
1102 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)1103 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1104 {
1105 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1106 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1107 GENMASK(25, 24));
1108 }
1109 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)1110 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1111 {
1112 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1113 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1114 GENMASK(27, 26));
1115 }
1116 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)1117 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1118 {
1119 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1120 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1121 BIT(28));
1122 }
1123 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1124 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1125 {
1126 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1127 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1128 BIT(29));
1129 }
1130 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1131 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1132 {
1133 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1134 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1135 BIT(30));
1136 }
1137 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1138 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1139 {
1140 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1141 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1142 BIT(31));
1143 }
1144
1145 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1146 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1147 {
1148 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1149 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1150 GENMASK(1, 0));
1151 }
1152
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1153 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1154 {
1155 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1156 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1157 GENMASK(3, 2));
1158 }
1159
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1160 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1161 {
1162 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1163 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1164 GENMASK(5, 4));
1165 }
1166
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1167 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1168 {
1169 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1170 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1171 GENMASK(7, 6));
1172 }
1173
1174 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1175 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1176 {
1177 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1178 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1179 GENMASK(7, 0));
1180 }
1181 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1182 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1183 {
1184 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1185 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1186 GENMASK(16, 8));
1187 }
1188 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1189 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1190 {
1191 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1192 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1193 BIT(17));
1194 }
1195 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1196 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1197 {
1198 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1199 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1200 GENMASK(19, 18));
1201 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1202 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1203 {
1204 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1205 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1206 GENMASK(21, 20));
1207 }
1208
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1209 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1210 {
1211 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1212 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1213 GENMASK(23, 22));
1214 }
1215 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1216 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1217 {
1218 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1219 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1220 GENMASK(27, 24));
1221 }
1222
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1223 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1224 {
1225 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1226 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1227 GENMASK(31, 30));
1228 }
1229 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1230 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1231 {
1232 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1233 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1234 GENMASK(2, 0));
1235 }
1236 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1237 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1238 {
1239 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1240 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1241 GENMASK(5, 3));
1242 }
1243 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1244 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1245 {
1246 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1247 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1248 GENMASK(7, 6));
1249 }
1250 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1251 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1252 {
1253 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1254 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1255 GENMASK(9, 8));
1256 }
1257 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1258 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1259 {
1260 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1261 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1262 GENMASK(11, 10));
1263 }
1264 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1265 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1266 {
1267 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1268 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1269 BIT(12));
1270 }
1271 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1272 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1273 {
1274 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1275 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1276 BIT(13));
1277 }
1278 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1279 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1280 {
1281 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1282 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1283 BIT(14));
1284 }
1285 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1286 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1287 {
1288 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1289 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1290 BIT(15));
1291 }
1292 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1293 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1294 {
1295 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1296 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1297 GENMASK(24, 16));
1298 }
1299 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1300 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1301 {
1302 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1303 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1304 GENMASK(27, 25));
1305 }
1306
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1307 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1308 {
1309 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1310 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1311 GENMASK(29, 28));
1312 }
1313
1314 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1315 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1316 {
1317 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1318 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1319 GENMASK(31, 30));
1320 }
1321
1322 struct rtw89_h2c_cctlinfo_ud_g7 {
1323 __le32 c0;
1324 __le32 w0;
1325 __le32 w1;
1326 __le32 w2;
1327 __le32 w3;
1328 __le32 w4;
1329 __le32 w5;
1330 __le32 w6;
1331 __le32 w7;
1332 __le32 w8;
1333 __le32 w9;
1334 __le32 w10;
1335 __le32 w11;
1336 __le32 w12;
1337 __le32 w13;
1338 __le32 w14;
1339 __le32 w15;
1340 __le32 m0;
1341 __le32 m1;
1342 __le32 m2;
1343 __le32 m3;
1344 __le32 m4;
1345 __le32 m5;
1346 __le32 m6;
1347 __le32 m7;
1348 __le32 m8;
1349 __le32 m9;
1350 __le32 m10;
1351 __le32 m11;
1352 __le32 m12;
1353 __le32 m13;
1354 __le32 m14;
1355 __le32 m15;
1356 } __packed;
1357
1358 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1359 #define CCTLINFO_G7_C0_OP BIT(7)
1360
1361 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1362 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1363 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1364 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1365 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1366 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1367 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1368 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1369 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1370 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1371 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1372 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1373 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1374 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1375 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1376 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1377 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1378 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1379 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1380 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1381 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1382 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1383 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1384 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1385 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1386 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1387 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1388 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1389 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1390 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1391 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1392 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1393 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1394 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1395 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1396 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1397 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1398 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1399 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1400 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1401 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1402 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1403 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1404 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1405 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1406 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1407 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1408 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1409 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1410 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1411 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1412 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1413 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1414 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1415 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1416 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1417 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1418 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1419 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1420 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1421 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1422 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1423 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1424 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1425 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1426 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1427 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1428 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1429 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1430 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1431 #define CCTLINFO_G7_W6_ULDL BIT(31)
1432 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1433 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1434 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1435 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1436 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1437 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1438 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1439 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1440 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1441 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1442 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1443 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1444 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1445 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1446 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1447 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1448 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1449 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1450 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1451 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1452 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1453 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1454 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1455 /* W9~13 are reserved */
1456 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1457 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1458 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1459 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1460 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1461 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1462 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1463 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1464
1465 struct rtw89_h2c_bcn_upd {
1466 __le32 w0;
1467 __le32 w1;
1468 __le32 w2;
1469 } __packed;
1470
1471 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1472 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1473 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1474 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1475 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1476 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1477 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1478 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1479 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1480 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1481 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1482 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1483 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1484 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1485 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1486 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1487 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1488 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1489 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1490 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1491
1492 struct rtw89_h2c_bcn_upd_be {
1493 __le32 w0;
1494 __le32 w1;
1495 __le32 w2;
1496 __le32 w3;
1497 __le32 w4;
1498 __le32 w5;
1499 __le32 w6;
1500 __le32 w7;
1501 __le32 w8;
1502 __le32 w9;
1503 __le32 w10;
1504 __le32 w11;
1505 __le32 w12;
1506 __le32 w13;
1507 __le32 w14;
1508 __le32 w15;
1509 __le32 w16;
1510 __le32 w17;
1511 __le32 w18;
1512 __le32 w19;
1513 __le32 w20;
1514 __le32 w21;
1515 __le32 w22;
1516 __le32 w23;
1517 __le32 w24;
1518 __le32 w25;
1519 __le32 w26;
1520 __le32 w27;
1521 __le32 w28;
1522 __le32 w29;
1523 } __packed;
1524
1525 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1526 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1527 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1528 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1529 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1530 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1531 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1532 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1533 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1534 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1535 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1536 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1537 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1538 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1539 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1540 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1541 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1542 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1543 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1544 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1545 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1546 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1547 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1548 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1549 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1550 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1551 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1552 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1553 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1554 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1555 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1556 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1557
SET_FWROLE_MAINTAIN_MACID(void * h2c,u32 val)1558 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1559 {
1560 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1561 }
1562
SET_FWROLE_MAINTAIN_SELF_ROLE(void * h2c,u32 val)1563 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1564 {
1565 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1566 }
1567
SET_FWROLE_MAINTAIN_UPD_MODE(void * h2c,u32 val)1568 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1569 {
1570 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1571 }
1572
SET_FWROLE_MAINTAIN_WIFI_ROLE(void * h2c,u32 val)1573 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1574 {
1575 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1576 }
1577
1578 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1579 RTW89_FW_N_AC_STA = 0,
1580 RTW89_FW_AX_STA = 1,
1581 RTW89_FW_BE_STA = 2,
1582 };
1583
1584 struct rtw89_h2c_join {
1585 __le32 w0;
1586 } __packed;
1587
1588 struct rtw89_h2c_join_v1 {
1589 __le32 w0;
1590 __le32 w1;
1591 __le32 w2;
1592 } __packed;
1593
1594 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1595 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1596 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1597 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1598 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1599 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1600 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1601 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1602 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1603 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1604 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1605 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1606 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1607 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1608 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1609 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1610 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1611 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1612 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1613 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1614 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1615 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1616 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1617 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1618
1619 struct rtw89_h2c_notify_dbcc {
1620 __le32 w0;
1621 } __packed;
1622
1623 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1624
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1625 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1626 {
1627 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1628 }
1629
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1630 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1631 {
1632 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1633 }
1634
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1635 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1636 {
1637 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1638 }
1639
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1640 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1641 {
1642 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1643 }
1644
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1645 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1646 {
1647 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1648 }
1649
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1650 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1651 {
1652 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1653 }
1654
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1655 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1656 {
1657 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1658 }
1659
SET_LOG_CFG_PATH(void * h2c,u32 val)1660 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1661 {
1662 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1663 }
1664
SET_LOG_CFG_COMP(void * h2c,u32 val)1665 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1666 {
1667 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1668 }
1669
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1670 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1671 {
1672 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1673 }
1674
1675 struct rtw89_h2c_ba_cam {
1676 __le32 w0;
1677 __le32 w1;
1678 } __packed;
1679
1680 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1681 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1682 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1683 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1684 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1685 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1686 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1687 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1688 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1689 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1690 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1691
1692 struct rtw89_h2c_ba_cam_v1 {
1693 __le32 w0;
1694 __le32 w1;
1695 } __packed;
1696
1697 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1698 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1699 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1700 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1701 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1702 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1703 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1704 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1705 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1706 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1707 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1708
1709 struct rtw89_h2c_ba_cam_init {
1710 __le32 w0;
1711 } __packed;
1712
1713 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1714 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1715 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1716
SET_LPS_PARM_MACID(void * h2c,u32 val)1717 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1718 {
1719 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1720 }
1721
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1722 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1723 {
1724 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1725 }
1726
SET_LPS_PARM_RLBM(void * h2c,u32 val)1727 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1728 {
1729 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1730 }
1731
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1732 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1733 {
1734 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1735 }
1736
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1737 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1738 {
1739 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1740 }
1741
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1742 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1743 {
1744 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1745 }
1746
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1747 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1748 {
1749 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1750 }
1751
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1752 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1753 {
1754 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1755 }
1756
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1757 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1758 {
1759 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1760 }
1761
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1762 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1763 {
1764 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1765 }
1766
1767 struct rtw89_h2c_lps_ch_info {
1768 struct {
1769 u8 pri_ch;
1770 u8 central_ch;
1771 u8 bw;
1772 u8 band;
1773 } __packed info[2];
1774
1775 __le32 mlo_dbcc_mode_lps;
1776 } __packed;
1777
RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void * cmd,u32 val)1778 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1779 {
1780 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1781 }
1782
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)1783 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1784 {
1785 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1786 }
1787
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)1788 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1789 {
1790 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1791 }
1792
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)1793 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1794 {
1795 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1796 }
1797
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)1798 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1799 {
1800 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1801 }
1802
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)1803 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1804 {
1805 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1806 }
1807
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)1808 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1809 {
1810 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1811 }
1812
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)1813 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1814 {
1815 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1816 }
1817
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)1818 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1819 {
1820 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1821 }
1822
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)1823 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1824 {
1825 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1826 }
1827
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)1828 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1829 {
1830 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1831 }
1832
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)1833 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1834 {
1835 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1836 }
1837
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)1838 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1839 {
1840 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1841 }
1842
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)1843 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1844 {
1845 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1846 }
1847
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)1848 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1849 {
1850 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1851 }
1852
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)1853 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1854 {
1855 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1856 }
1857
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)1858 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1859 {
1860 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1861 }
1862
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)1863 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1864 {
1865 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1866 }
1867
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)1868 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1869 {
1870 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1871 }
1872
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)1873 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1874 {
1875 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1876 }
1877
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)1878 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1879 {
1880 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1881 }
1882
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)1883 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1884 {
1885 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1886 }
1887
1888 struct rtw89_h2c_wow_global {
1889 __le32 w0;
1890 struct rtw89_wow_key_info key_info;
1891 } __packed;
1892
1893 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1894 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1895 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1896 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1897 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1898 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1899 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1900
1901 #define RTW89_MAX_SUPPORT_NL_NUM 16
1902 struct rtw89_h2c_cfg_nlo {
1903 __le32 w0;
1904 u8 nlo_cnt;
1905 u8 rsvd[3];
1906 __le32 patterncheck;
1907 __le32 rsvd1;
1908 __le32 rsvd2;
1909 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
1910 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
1911 u8 rsvd3[24];
1912 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
1913 } __packed;
1914
1915 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1916 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1917 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
1918
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void * h2c,u32 val)1919 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
1920 {
1921 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1922 }
1923
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void * h2c,u32 val)1924 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
1925 {
1926 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1927 }
1928
RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void * h2c,u32 val)1929 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
1930 {
1931 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1932 }
1933
RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void * h2c,u32 val)1934 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
1935 {
1936 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1937 }
1938
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void * h2c,u32 val)1939 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
1940 {
1941 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
1942 }
1943
RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void * h2c,u32 val)1944 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
1945 {
1946 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
1947 }
1948
RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void * h2c,u32 val)1949 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
1950 {
1951 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
1952 }
1953
RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void * h2c,u32 val)1954 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
1955 {
1956 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
1957 }
1958
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void * h2c,u32 val)1959 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
1960 {
1961 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1962 }
1963
RTW89_SET_WOW_CAM_UPD_R_W(void * h2c,u32 val)1964 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
1965 {
1966 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1967 }
1968
RTW89_SET_WOW_CAM_UPD_IDX(void * h2c,u32 val)1969 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
1970 {
1971 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
1972 }
1973
RTW89_SET_WOW_CAM_UPD_WKFM1(void * h2c,u32 val)1974 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
1975 {
1976 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
1977 }
1978
RTW89_SET_WOW_CAM_UPD_WKFM2(void * h2c,u32 val)1979 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
1980 {
1981 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
1982 }
1983
RTW89_SET_WOW_CAM_UPD_WKFM3(void * h2c,u32 val)1984 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
1985 {
1986 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
1987 }
1988
RTW89_SET_WOW_CAM_UPD_WKFM4(void * h2c,u32 val)1989 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
1990 {
1991 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
1992 }
1993
RTW89_SET_WOW_CAM_UPD_CRC(void * h2c,u32 val)1994 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
1995 {
1996 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
1997 }
1998
RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void * h2c,u32 val)1999 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2000 {
2001 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2002 }
2003
RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void * h2c,u32 val)2004 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2005 {
2006 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2007 }
2008
RTW89_SET_WOW_CAM_UPD_UC(void * h2c,u32 val)2009 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2010 {
2011 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2012 }
2013
RTW89_SET_WOW_CAM_UPD_MC(void * h2c,u32 val)2014 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2015 {
2016 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2017 }
2018
RTW89_SET_WOW_CAM_UPD_BC(void * h2c,u32 val)2019 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2020 {
2021 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2022 }
2023
RTW89_SET_WOW_CAM_UPD_VALID(void * h2c,u32 val)2024 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2025 {
2026 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2027 }
2028
2029 struct rtw89_h2c_wow_gtk_ofld {
2030 __le32 w0;
2031 __le32 w1;
2032 struct rtw89_wow_gtk_info gtk_info;
2033 } __packed;
2034
2035 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2036 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2037 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2038 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2039 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2040 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2041 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2042 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2043 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2044 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2045
2046 struct rtw89_h2c_arp_offload {
2047 __le32 w0;
2048 __le32 w1;
2049 } __packed;
2050
2051 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2052 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2053 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2054 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2055 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2056
2057 enum rtw89_btc_btf_h2c_class {
2058 BTFC_SET = 0x10,
2059 BTFC_GET = 0x11,
2060 BTFC_FW_EVENT = 0x12,
2061 };
2062
2063 enum rtw89_btc_btf_set {
2064 SET_REPORT_EN = 0x0,
2065 SET_SLOT_TABLE,
2066 SET_MREG_TABLE,
2067 SET_CX_POLICY,
2068 SET_GPIO_DBG,
2069 SET_DRV_INFO,
2070 SET_DRV_EVENT,
2071 SET_BT_WREG_ADDR,
2072 SET_BT_WREG_VAL,
2073 SET_BT_RREG_ADDR,
2074 SET_BT_WL_CH_INFO,
2075 SET_BT_INFO_REPORT,
2076 SET_BT_IGNORE_WLAN_ACT,
2077 SET_BT_TX_PWR,
2078 SET_BT_LNA_CONSTRAIN,
2079 SET_BT_QUERY_DEV_LIST,
2080 SET_BT_QUERY_DEV_INFO,
2081 SET_BT_PSD_REPORT,
2082 SET_H2C_TEST,
2083 SET_IOFLD_RF,
2084 SET_IOFLD_BB,
2085 SET_IOFLD_MAC,
2086 SET_IOFLD_SCBD,
2087 SET_H2C_MACRO,
2088 SET_MAX1,
2089 };
2090
2091 enum rtw89_btc_cxdrvinfo {
2092 CXDRVINFO_INIT = 0,
2093 CXDRVINFO_ROLE,
2094 CXDRVINFO_DBCC,
2095 CXDRVINFO_SMAP,
2096 CXDRVINFO_RFK,
2097 CXDRVINFO_RUN,
2098 CXDRVINFO_CTRL,
2099 CXDRVINFO_SCAN,
2100 CXDRVINFO_TRX, /* WL traffic to WL fw */
2101 CXDRVINFO_TXPWR,
2102 CXDRVINFO_FDDT,
2103 CXDRVINFO_MLO,
2104 CXDRVINFO_OSI,
2105 CXDRVINFO_MAX,
2106 };
2107
2108 enum rtw89_scan_mode {
2109 RTW89_SCAN_IMMEDIATE,
2110 RTW89_SCAN_DELAY,
2111 };
2112
2113 enum rtw89_scan_type {
2114 RTW89_SCAN_ONCE,
2115 RTW89_SCAN_NORMAL,
2116 RTW89_SCAN_NORMAL_SLOW,
2117 RTW89_SCAN_SEAMLESS,
2118 RTW89_SCAN_MAX,
2119 };
2120
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2121 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2122 {
2123 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2124 }
2125
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2126 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2127 {
2128 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2129 }
2130
2131 struct rtw89_h2c_cxhdr {
2132 u8 type;
2133 u8 len;
2134 } __packed;
2135
2136 struct rtw89_h2c_cxhdr_v7 {
2137 u8 type;
2138 u8 ver;
2139 u8 len;
2140 } __packed;
2141
2142 struct rtw89_h2c_cxctrl_v7 {
2143 struct rtw89_h2c_cxhdr_v7 hdr;
2144 struct rtw89_btc_ctrl_v7 ctrl;
2145 } __packed;
2146
2147 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2148 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2149
2150 struct rtw89_btc_wl_role_info_v7_u8 {
2151 u8 connect_cnt;
2152 u8 link_mode;
2153 u8 link_mode_chg;
2154 u8 p2p_2g;
2155
2156 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
2157 } __packed;
2158
2159 struct rtw89_btc_wl_role_info_v7_u32 {
2160 __le32 role_map;
2161 __le32 mrole_type;
2162 __le32 mrole_noa_duration;
2163 __le32 dbcc_en;
2164 __le32 dbcc_chg;
2165 __le32 dbcc_2g_phy;
2166 } __packed;
2167
2168 struct rtw89_h2c_cxrole_v7 {
2169 struct rtw89_h2c_cxhdr_v7 hdr;
2170 struct rtw89_btc_wl_role_info_v7_u8 _u8;
2171 struct rtw89_btc_wl_role_info_v7_u32 _u32;
2172 } __packed;
2173
2174 struct rtw89_btc_wl_role_info_v8_u8 {
2175 u8 connect_cnt;
2176 u8 link_mode;
2177 u8 link_mode_chg;
2178 u8 p2p_2g;
2179
2180 u8 pta_req_band;
2181 u8 dbcc_en;
2182 u8 dbcc_chg;
2183 u8 dbcc_2g_phy;
2184
2185 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2186 } __packed;
2187
2188 struct rtw89_btc_wl_role_info_v8_u32 {
2189 __le32 role_map;
2190 __le32 mrole_type;
2191 __le32 mrole_noa_duration;
2192 } __packed;
2193
2194 struct rtw89_h2c_cxrole_v8 {
2195 struct rtw89_h2c_cxhdr_v7 hdr;
2196 struct rtw89_btc_wl_role_info_v8_u8 _u8;
2197 struct rtw89_btc_wl_role_info_v8_u32 _u32;
2198 } __packed;
2199
2200 struct rtw89_h2c_cxinit {
2201 struct rtw89_h2c_cxhdr hdr;
2202 u8 ant_type;
2203 u8 ant_num;
2204 u8 ant_iso;
2205 u8 ant_info;
2206 u8 mod_rfe;
2207 u8 mod_cv;
2208 u8 mod_info;
2209 u8 mod_adie_kt;
2210 u8 wl_gch;
2211 u8 info;
2212 u8 rsvd;
2213 u8 rsvd1;
2214 } __packed;
2215
2216 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2217 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2218 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2219 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2220
2221 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2222 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2223 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2224 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2225
2226 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2227 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2228 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2229 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2230 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2231
2232 struct rtw89_h2c_cxinit_v7 {
2233 struct rtw89_h2c_cxhdr_v7 hdr;
2234 struct rtw89_btc_init_info_v7 init;
2235 } __packed;
2236
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2237 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2238 {
2239 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2240 }
2241
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2242 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2243 {
2244 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2245 }
2246
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2247 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2248 {
2249 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2250 }
2251
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2252 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2253 {
2254 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2255 }
2256
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2257 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2258 {
2259 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2260 }
2261
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2262 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2263 {
2264 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2265 }
2266
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2267 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2268 {
2269 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2270 }
2271
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2272 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2273 {
2274 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2275 }
2276
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2277 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2278 {
2279 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2280 }
2281
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2282 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2283 {
2284 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2285 }
2286
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2287 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2288 {
2289 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2290 }
2291
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2292 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2293 {
2294 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2295 }
2296
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2297 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2298 {
2299 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2300 }
2301
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2302 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2303 {
2304 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2305 }
2306
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2307 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2308 {
2309 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2310 }
2311
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2312 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2313 {
2314 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2315 }
2316
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2317 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2318 {
2319 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2320 }
2321
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2322 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2323 {
2324 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2325 }
2326
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2327 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2328 {
2329 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2330 }
2331
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2332 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2333 {
2334 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2335 }
2336
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2337 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2338 {
2339 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2340 }
2341
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2342 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2343 {
2344 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2345 }
2346
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2347 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2348 {
2349 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2350 }
2351
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2352 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2353 {
2354 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2355 }
2356
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2357 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2358 {
2359 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2360 }
2361
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2362 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2363 {
2364 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2365 }
2366
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2367 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2368 {
2369 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2370 }
2371
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2372 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2373 {
2374 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2375 }
2376
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2377 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2378 {
2379 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2380 }
2381
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2382 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2383 {
2384 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2385 }
2386
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2387 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2388 {
2389 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2390 }
2391
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2392 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2393 {
2394 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2395 }
2396
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2397 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2398 {
2399 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2400 }
2401
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2402 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2403 {
2404 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2405 }
2406
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2407 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2408 {
2409 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2410 }
2411
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2412 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2413 {
2414 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2415 }
2416
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2417 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2418 {
2419 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2420 }
2421
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2422 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2423 {
2424 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2425 }
2426
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2427 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2428 {
2429 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2430 }
2431
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2432 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2433 {
2434 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2435 }
2436
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2437 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2438 {
2439 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2440 }
2441
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2442 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2443 {
2444 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2445 }
2446
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2447 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2448 {
2449 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2450 }
2451
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2452 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2453 {
2454 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2455 }
2456
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2457 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2458 {
2459 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2460 }
2461
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2462 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2463 {
2464 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2465 }
2466
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2467 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2468 {
2469 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2470 }
2471
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2472 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2473 {
2474 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2475 }
2476
RTW89_SET_FWCMD_CXTRX_TXLV(void * cmd,u8 val)2477 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2478 {
2479 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2480 }
2481
RTW89_SET_FWCMD_CXTRX_RXLV(void * cmd,u8 val)2482 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2483 {
2484 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2485 }
2486
RTW89_SET_FWCMD_CXTRX_WLRSSI(void * cmd,u8 val)2487 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2488 {
2489 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2490 }
2491
RTW89_SET_FWCMD_CXTRX_BTRSSI(void * cmd,u8 val)2492 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2493 {
2494 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2495 }
2496
RTW89_SET_FWCMD_CXTRX_TXPWR(void * cmd,s8 val)2497 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2498 {
2499 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2500 }
2501
RTW89_SET_FWCMD_CXTRX_RXGAIN(void * cmd,s8 val)2502 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2503 {
2504 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2505 }
2506
RTW89_SET_FWCMD_CXTRX_BTTXPWR(void * cmd,s8 val)2507 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2508 {
2509 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2510 }
2511
RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void * cmd,s8 val)2512 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2513 {
2514 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2515 }
2516
RTW89_SET_FWCMD_CXTRX_CN(void * cmd,u8 val)2517 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2518 {
2519 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2520 }
2521
RTW89_SET_FWCMD_CXTRX_NHM(void * cmd,s8 val)2522 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2523 {
2524 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2525 }
2526
RTW89_SET_FWCMD_CXTRX_BTPROFILE(void * cmd,u8 val)2527 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2528 {
2529 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2530 }
2531
RTW89_SET_FWCMD_CXTRX_RSVD2(void * cmd,u8 val)2532 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2533 {
2534 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2535 }
2536
RTW89_SET_FWCMD_CXTRX_TXRATE(void * cmd,u16 val)2537 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2538 {
2539 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2540 }
2541
RTW89_SET_FWCMD_CXTRX_RXRATE(void * cmd,u16 val)2542 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2543 {
2544 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2545 }
2546
RTW89_SET_FWCMD_CXTRX_TXTP(void * cmd,u32 val)2547 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2548 {
2549 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2550 }
2551
RTW89_SET_FWCMD_CXTRX_RXTP(void * cmd,u32 val)2552 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2553 {
2554 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2555 }
2556
RTW89_SET_FWCMD_CXTRX_RXERRRA(void * cmd,u32 val)2557 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2558 {
2559 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2560 }
2561
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2562 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2563 {
2564 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2565 }
2566
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2567 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2568 {
2569 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2570 }
2571
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2572 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2573 {
2574 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2575 }
2576
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2577 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2578 {
2579 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2580 }
2581
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2582 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2583 {
2584 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2585 }
2586
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2587 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2588 {
2589 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2590 }
2591
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2592 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2593 {
2594 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2595 }
2596
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2597 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2598 {
2599 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2600 }
2601
2602 struct rtw89_h2c_chinfo_elem {
2603 __le32 w0;
2604 __le32 w1;
2605 __le32 w2;
2606 __le32 w3;
2607 __le32 w4;
2608 __le32 w5;
2609 __le32 w6;
2610 } __packed;
2611
2612 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2613 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2614 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2615 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2616 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2617 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2618 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2619 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2620 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2621 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2622 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2623 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2624 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2625 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2626 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2627 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2628 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2629 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2630 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2631 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2632 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2633 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2634 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2635 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2636
2637 struct rtw89_h2c_chinfo_elem_be {
2638 __le32 w0;
2639 __le32 w1;
2640 __le32 w2;
2641 __le32 w3;
2642 __le32 w4;
2643 __le32 w5;
2644 __le32 w6;
2645 } __packed;
2646
2647 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2648 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2649 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2650 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2651 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2652 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2653 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2654 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2655 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2656 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2657 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2658 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2659 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2660 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2661 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2662 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2663 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2664 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2665 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2666 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2667 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2668 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2669 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2670 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2671 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2672 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2673 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2674 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2675 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2676
2677 struct rtw89_h2c_chinfo {
2678 u8 ch_num;
2679 u8 elem_size;
2680 u8 arg;
2681 u8 rsvd0;
2682 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2683 } __packed;
2684
2685 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2686 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2687
2688 struct rtw89_h2c_scanofld {
2689 __le32 w0;
2690 __le32 w1;
2691 __le32 w2;
2692 __le32 tsf_high;
2693 __le32 tsf_low;
2694 __le32 w5;
2695 __le32 w6;
2696 } __packed;
2697
2698 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2699 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2700 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2701 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2702 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2703 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2704 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2705 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2706 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2707 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2708 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2709 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2710 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2711 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2712 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2713 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2714 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
2715 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
2716
2717 struct rtw89_h2c_scanofld_be_macc_role {
2718 __le32 w0;
2719 } __packed;
2720
2721 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2722 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2723 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2724 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2725
2726 struct rtw89_h2c_scanofld_be_opch {
2727 __le32 w0;
2728 __le32 w1;
2729 __le32 w2;
2730 __le32 w3;
2731 } __packed;
2732
2733 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2734 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2735 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2736 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2737 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2738 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2739 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2740 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2741 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2742 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2743 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2744 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2745 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2746 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2747 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2748 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2749 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2750 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2751 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2752
2753 struct rtw89_h2c_scanofld_be {
2754 __le32 w0;
2755 __le32 w1;
2756 __le32 w2;
2757 __le32 w3;
2758 __le32 w4;
2759 __le32 w5;
2760 __le32 w6;
2761 __le32 w7;
2762 __le32 w8;
2763 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
2764 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
2765 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
2766 } __packed;
2767
2768 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2769 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2770 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2771 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2772 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2773 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2774 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2775 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2776 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2777 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2778 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2779 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2780 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2781 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2782 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2783 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2784 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2785 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2786 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2787 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2788 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2789 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2790 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2791 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2792 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2793 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
2794 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
2795 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
2796 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
2797 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
2798 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
2799
2800 struct rtw89_h2c_fwips {
2801 __le32 w0;
2802 } __packed;
2803
2804 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
2805 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2806
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)2807 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2808 {
2809 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2810 }
2811
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)2812 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2813 {
2814 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2815 }
2816
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)2817 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2818 {
2819 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2820 }
2821
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)2822 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2823 {
2824 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2825 }
2826
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)2827 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2828 {
2829 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2830 }
2831
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)2832 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2833 {
2834 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2835 }
2836
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)2837 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2838 {
2839 *((__le32 *)cmd + 1) = val;
2840 }
2841
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)2842 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2843 {
2844 *((__le32 *)cmd + 2) = val;
2845 }
2846
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)2847 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2848 {
2849 *((__le32 *)cmd + 3) = val;
2850 }
2851
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)2852 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2853 {
2854 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2855 }
2856
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)2857 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2858 {
2859 u8 ctwnd;
2860
2861 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2862 return;
2863 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2864 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2865 }
2866
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)2867 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2868 {
2869 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2870 }
2871
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)2872 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2873 {
2874 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2875 }
2876
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)2877 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2878 {
2879 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2880 }
2881
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)2882 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2883 {
2884 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2885 }
2886
2887 enum rtw89_fw_mcc_c2h_rpt_cfg {
2888 RTW89_FW_MCC_C2H_RPT_OFF = 0,
2889 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
2890 RTW89_FW_MCC_C2H_RPT_ALL = 2,
2891 };
2892
2893 struct rtw89_fw_mcc_add_req {
2894 u8 macid;
2895 u8 central_ch_seg0;
2896 u8 central_ch_seg1;
2897 u8 primary_ch;
2898 enum rtw89_bandwidth bandwidth: 4;
2899 u32 group: 2;
2900 u32 c2h_rpt: 2;
2901 u32 dis_tx_null: 1;
2902 u32 dis_sw_retry: 1;
2903 u32 in_curr_ch: 1;
2904 u32 sw_retry_count: 3;
2905 u32 tx_null_early: 4;
2906 u32 btc_in_2g: 1;
2907 u32 pta_en: 1;
2908 u32 rfk_by_pass: 1;
2909 u32 ch_band_type: 2;
2910 u32 rsvd0: 9;
2911 u32 duration;
2912 u8 courtesy_en;
2913 u8 courtesy_num;
2914 u8 courtesy_target;
2915 u8 rsvd1;
2916 };
2917
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)2918 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2919 {
2920 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2921 }
2922
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)2923 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2924 {
2925 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2926 }
2927
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)2928 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2929 {
2930 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2931 }
2932
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)2933 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2934 {
2935 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2936 }
2937
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)2938 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2939 {
2940 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2941 }
2942
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)2943 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2944 {
2945 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2946 }
2947
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)2948 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2949 {
2950 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2951 }
2952
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)2953 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2954 {
2955 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2956 }
2957
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)2958 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2959 {
2960 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2961 }
2962
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)2963 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2964 {
2965 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2966 }
2967
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)2968 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2969 {
2970 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2971 }
2972
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)2973 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2974 {
2975 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2976 }
2977
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)2978 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2979 {
2980 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2981 }
2982
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)2983 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
2984 {
2985 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
2986 }
2987
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)2988 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
2989 {
2990 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
2991 }
2992
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)2993 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
2994 {
2995 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
2996 }
2997
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)2998 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
2999 {
3000 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3001 }
3002
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)3003 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3004 {
3005 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3006 }
3007
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)3008 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3009 {
3010 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3011 }
3012
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)3013 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3014 {
3015 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3016 }
3017
3018 enum rtw89_fw_mcc_old_group_actions {
3019 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3020 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3021 };
3022
3023 struct rtw89_fw_mcc_start_req {
3024 u32 group: 2;
3025 u32 btc_in_group: 1;
3026 u32 old_group_action: 2;
3027 u32 old_group: 2;
3028 u32 rsvd0: 9;
3029 u32 notify_cnt: 3;
3030 u32 rsvd1: 2;
3031 u32 notify_rxdbg_en: 1;
3032 u32 rsvd2: 2;
3033 u32 macid: 8;
3034 u32 tsf_low;
3035 u32 tsf_high;
3036 };
3037
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)3038 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3039 {
3040 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3041 }
3042
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)3043 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3044 {
3045 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3046 }
3047
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)3048 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3049 {
3050 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3051 }
3052
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)3053 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3054 {
3055 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3056 }
3057
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)3058 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3059 {
3060 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3061 }
3062
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)3063 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3064 {
3065 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3066 }
3067
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)3068 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3069 {
3070 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3071 }
3072
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)3073 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3074 {
3075 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3076 }
3077
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3078 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3079 {
3080 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3081 }
3082
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3083 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3084 {
3085 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3086 }
3087
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3088 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3089 {
3090 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3091 }
3092
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3093 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3094 {
3095 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3096 }
3097
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3098 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3099 {
3100 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3101 }
3102
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3103 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3104 {
3105 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3106 }
3107
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3108 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3109 {
3110 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3111 }
3112
3113 struct rtw89_fw_mcc_tsf_req {
3114 u8 group: 2;
3115 u8 rsvd0: 6;
3116 u8 macid_x;
3117 u8 macid_y;
3118 u8 rsvd1;
3119 };
3120
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3121 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3122 {
3123 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3124 }
3125
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3126 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3127 {
3128 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3129 }
3130
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3131 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3132 {
3133 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3134 }
3135
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3136 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3137 {
3138 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3139 }
3140
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3141 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3142 {
3143 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3144 }
3145
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3146 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3147 {
3148 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3149 }
3150
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3151 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3152 u8 *bitmap, u8 len)
3153 {
3154 memcpy((__le32 *)cmd + 1, bitmap, len);
3155 }
3156
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3157 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3158 {
3159 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3160 }
3161
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3162 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3163 {
3164 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3165 }
3166
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3167 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3168 {
3169 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3170 }
3171
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3172 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3173 {
3174 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3175 }
3176
3177 struct rtw89_fw_mcc_duration {
3178 u32 group: 2;
3179 u32 btc_in_group: 1;
3180 u32 rsvd0: 5;
3181 u32 start_macid: 8;
3182 u32 macid_x: 8;
3183 u32 macid_y: 8;
3184 u32 start_tsf_low;
3185 u32 start_tsf_high;
3186 u32 duration_x;
3187 u32 duration_y;
3188 };
3189
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3190 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3191 {
3192 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3193 }
3194
3195 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3196 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3197 {
3198 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3199 }
3200
3201 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3202 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3203 {
3204 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3205 }
3206
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3207 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3208 {
3209 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3210 }
3211
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3212 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3213 {
3214 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3215 }
3216
3217 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3218 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3219 {
3220 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3221 }
3222
3223 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3224 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3225 {
3226 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3227 }
3228
3229 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3230 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3231 {
3232 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3233 }
3234
3235 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3236 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3237 {
3238 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3239 }
3240
3241 enum rtw89_h2c_mrc_sch_types {
3242 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3243 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3244 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3245 };
3246
3247 enum rtw89_h2c_mrc_role_types {
3248 RTW89_H2C_MRC_ROLE_WIFI = 0,
3249 RTW89_H2C_MRC_ROLE_BT = 1,
3250 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3251 };
3252
3253 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3254 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3255
3256 struct rtw89_fw_mrc_add_slot_arg {
3257 u16 duration; /* unit: TU */
3258 bool courtesy_en;
3259 u8 courtesy_period;
3260 u8 courtesy_target; /* slot idx */
3261
3262 unsigned int role_num;
3263 struct {
3264 enum rtw89_h2c_mrc_role_types role_type;
3265 bool is_master;
3266 bool en_tx_null;
3267 enum rtw89_band band;
3268 enum rtw89_bandwidth bw;
3269 u8 macid;
3270 u8 central_ch;
3271 u8 primary_ch;
3272 u8 null_early; /* unit: TU */
3273
3274 /* if MLD, for macid: [0, chip::support_mld_num)
3275 * otherwise, for macid: [0, 32)
3276 */
3277 u32 macid_main_bitmap;
3278 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3279 u32 macid_paired_bitmap;
3280 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3281 };
3282
3283 struct rtw89_fw_mrc_add_arg {
3284 u8 sch_idx;
3285 enum rtw89_h2c_mrc_sch_types sch_type;
3286 bool btc_in_sch;
3287
3288 unsigned int slot_num;
3289 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3290 };
3291
3292 struct rtw89_h2c_mrc_add_role {
3293 __le32 w0;
3294 __le32 w1;
3295 __le32 w2;
3296 __le32 macid_main_bitmap;
3297 __le32 macid_paired_bitmap;
3298 } __packed;
3299
3300 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3301 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3302 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3303 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3304 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3305 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3306 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3307 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3308 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3309 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3310 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3311 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3312 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3313 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3314 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3315 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3316
3317 struct rtw89_h2c_mrc_add_slot {
3318 __le32 w0;
3319 __le32 w1;
3320 struct rtw89_h2c_mrc_add_role roles[];
3321 } __packed;
3322
3323 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3324 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3325 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3326 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3327 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3328
3329 struct rtw89_h2c_mrc_add {
3330 __le32 w0;
3331 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3332 * are other flexible array inside it. We cannot access them correctly
3333 * through this struct. So, in case misusing, we don't really declare
3334 * it here.
3335 */
3336 } __packed;
3337
3338 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3339 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3340 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3341 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3342
3343 enum rtw89_h2c_mrc_start_actions {
3344 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3345 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3346 };
3347
3348 struct rtw89_fw_mrc_start_arg {
3349 u8 sch_idx;
3350 u8 old_sch_idx;
3351 u64 start_tsf;
3352 enum rtw89_h2c_mrc_start_actions action;
3353 };
3354
3355 struct rtw89_h2c_mrc_start {
3356 __le32 w0;
3357 __le32 start_tsf_low;
3358 __le32 start_tsf_high;
3359 } __packed;
3360
3361 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3362 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3363 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3364
3365 struct rtw89_h2c_mrc_del {
3366 __le32 w0;
3367 } __packed;
3368
3369 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3370 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3371 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3372 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3373 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3374 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3375
3376 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3377
3378 struct rtw89_fw_mrc_req_tsf_arg {
3379 unsigned int num;
3380 struct {
3381 u8 band;
3382 u8 port;
3383 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3384 };
3385
3386 struct rtw89_h2c_mrc_req_tsf {
3387 u8 req_tsf_num;
3388 u8 infos[] __counted_by(req_tsf_num);
3389 } __packed;
3390
3391 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3392 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3393
3394 enum rtw89_h2c_mrc_upd_bitmap_actions {
3395 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3396 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3397 };
3398
3399 struct rtw89_fw_mrc_upd_bitmap_arg {
3400 u8 sch_idx;
3401 u8 macid;
3402 u8 client_macid;
3403 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3404 };
3405
3406 struct rtw89_h2c_mrc_upd_bitmap {
3407 __le32 w0;
3408 __le32 w1;
3409 } __packed;
3410
3411 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3412 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3413 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3414 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3415
3416 struct rtw89_fw_mrc_sync_arg {
3417 u8 offset; /* unit: TU */
3418 struct {
3419 u8 band;
3420 u8 port;
3421 } src, dest;
3422 };
3423
3424 struct rtw89_h2c_mrc_sync {
3425 __le32 w0;
3426 __le32 w1;
3427 } __packed;
3428
3429 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3430 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3431 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3432 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3433 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3434 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3435
3436 struct rtw89_fw_mrc_upd_duration_arg {
3437 u8 sch_idx;
3438 u64 start_tsf;
3439
3440 unsigned int slot_num;
3441 struct {
3442 u8 slot_idx;
3443 u16 duration; /* unit: TU */
3444 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3445 };
3446
3447 struct rtw89_h2c_mrc_upd_duration {
3448 __le32 w0;
3449 __le32 start_tsf_low;
3450 __le32 start_tsf_high;
3451 __le32 slots[];
3452 } __packed;
3453
3454 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3455 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3456 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3457 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3458 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3459
3460 struct rtw89_h2c_wow_aoac {
3461 __le32 w0;
3462 } __packed;
3463
3464 #define RTW89_C2H_HEADER_LEN 8
3465
3466 struct rtw89_c2h_hdr {
3467 __le32 w0;
3468 __le32 w1;
3469 } __packed;
3470
3471 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3472 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3473 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3474 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3475
3476 struct rtw89_fw_c2h_attr {
3477 u8 category;
3478 u8 class;
3479 u8 func;
3480 u16 len;
3481 };
3482
RTW89_SKB_C2H_CB(struct sk_buff * skb)3483 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3484 {
3485 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3486
3487 return (struct rtw89_fw_c2h_attr *)skb->cb;
3488 }
3489
3490 struct rtw89_c2h_done_ack {
3491 __le32 w0;
3492 __le32 w1;
3493 __le32 w2;
3494 } __packed;
3495
3496 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3497 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3498 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3499 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3500 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3501
3502 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3503 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3504 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3505 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3506 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3507 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3508 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3509 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3510
3511 struct rtw89_fw_c2h_log_fmt {
3512 __le16 signature;
3513 u8 feature;
3514 u8 syntax;
3515 __le32 fmt_id;
3516 u8 file_num;
3517 __le16 line_num;
3518 u8 argc;
3519 union {
3520 DECLARE_FLEX_ARRAY(u8, raw);
3521 DECLARE_FLEX_ARRAY(__le32, argv);
3522 } __packed u;
3523 } __packed;
3524
3525 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3526 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3527 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3528 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3529 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3530
3531 struct rtw89_c2h_mac_bcnfltr_rpt {
3532 __le32 w0;
3533 __le32 w1;
3534 __le32 w2;
3535 } __packed;
3536
3537 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3538 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3539 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3540 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3541
3542 struct rtw89_c2h_ra_rpt {
3543 struct rtw89_c2h_hdr hdr;
3544 __le32 w2;
3545 __le32 w3;
3546 } __packed;
3547
3548 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3549 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3550 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3551 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3552 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3553 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3554 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3555 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3556 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3557
3558 /* For WiFi 6 chips:
3559 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3560 * HT-new: [6:5]: NA, [4:0]: MCS
3561 * For WiFi 7 chips (V1):
3562 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3563 */
3564 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3565 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3566 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3567 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3568 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3569 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3570 FIELD_PREP(GENMASK(2, 0), mcs))
3571
3572 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3573 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3574 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3575 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3576 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3577 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3578
3579 struct rtw89_c2h_scanofld {
3580 __le32 w0;
3581 __le32 w1;
3582 __le32 w2;
3583 __le32 w3;
3584 __le32 w4;
3585 __le32 w5;
3586 __le32 w6;
3587 __le32 w7;
3588 } __packed;
3589
3590 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3591 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3592 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3593 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3594 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3595 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3596 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3597 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3598 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3599 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3600 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3601 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3602
3603 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3604 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3605 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3606 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3607
3608 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3609 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3610 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3611 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3612 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3613 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3614
3615 struct rtw89_mac_mcc_tsf_rpt {
3616 u32 macid_x;
3617 u32 macid_y;
3618 u32 tsf_x_low;
3619 u32 tsf_x_high;
3620 u32 tsf_y_low;
3621 u32 tsf_y_high;
3622 };
3623
3624 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3625
3626 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3627 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3628 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3629 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3630 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3631 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3632 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3633 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3634 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3635 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3636 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3637 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3638 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3639 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3640
3641 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3642 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3643 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3644 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3645 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3646 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3647 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3648 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3649 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3650 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3651
3652 struct rtw89_mac_mrc_tsf_rpt {
3653 unsigned int num;
3654 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3655 };
3656
3657 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3658
3659 struct rtw89_c2h_mrc_tsf_rpt_info {
3660 __le32 tsf_low;
3661 __le32 tsf_high;
3662 } __packed;
3663
3664 struct rtw89_c2h_mrc_tsf_rpt {
3665 struct rtw89_c2h_hdr hdr;
3666 __le32 w2;
3667 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3668 } __packed;
3669
3670 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3671
3672 struct rtw89_c2h_mrc_status_rpt {
3673 struct rtw89_c2h_hdr hdr;
3674 __le32 w2;
3675 __le32 tsf_low;
3676 __le32 tsf_high;
3677 } __packed;
3678
3679 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3680 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3681
3682 struct rtw89_c2h_pkt_ofld_rsp {
3683 __le32 w0;
3684 __le32 w1;
3685 __le32 w2;
3686 } __packed;
3687
3688 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3689 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3690 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3691
3692 struct rtw89_c2h_wow_aoac_report {
3693 struct rtw89_c2h_hdr c2h_hdr;
3694 u8 rpt_ver;
3695 u8 sec_type;
3696 u8 key_idx;
3697 u8 pattern_idx;
3698 u8 rekey_ok;
3699 u8 rsvd1[3];
3700 u8 ptk_tx_iv[8];
3701 u8 eapol_key_replay_count[8];
3702 u8 gtk[32];
3703 u8 ptk_rx_iv[8];
3704 u8 gtk_rx_iv[4][8];
3705 __le64 igtk_key_id;
3706 __le64 igtk_ipn;
3707 u8 igtk[32];
3708 u8 csa_pri_ch;
3709 u8 csa_bw_ch_offset;
3710 u8 csa_ch_band_chsw_failed;
3711 u8 csa_rsvd1;
3712 } __packed;
3713
3714 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3715
3716 struct rtw89_h2c_bcnfltr {
3717 __le32 w0;
3718 } __packed;
3719
3720 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3721 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3722 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3723 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3724 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3725 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3726 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3727 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3728
3729 struct rtw89_h2c_ofld_rssi {
3730 __le32 w0;
3731 __le32 w1;
3732 } __packed;
3733
3734 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3735 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3736 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3737
3738 struct rtw89_h2c_ofld {
3739 __le32 w0;
3740 } __packed;
3741
3742 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3743 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3744 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3745
3746 #define RTW89_MFW_SIG 0xFF
3747
3748 struct rtw89_mfw_info {
3749 u8 cv;
3750 u8 type; /* enum rtw89_fw_type */
3751 u8 mp;
3752 u8 rsvd;
3753 __le32 shift;
3754 __le32 size;
3755 u8 rsvd2[4];
3756 } __packed;
3757
3758 struct rtw89_mfw_hdr {
3759 u8 sig; /* RTW89_MFW_SIG */
3760 u8 fw_nr;
3761 u8 rsvd0[2];
3762 struct {
3763 u8 major;
3764 u8 minor;
3765 u8 sub;
3766 u8 idx;
3767 } ver;
3768 u8 rsvd1[8];
3769 struct rtw89_mfw_info info[];
3770 } __packed;
3771
3772 struct rtw89_fw_logsuit_hdr {
3773 __le32 rsvd;
3774 __le32 count;
3775 __le32 ids[];
3776 } __packed;
3777
3778 #define RTW89_FW_ELEMENT_ALIGN 16
3779
3780 enum rtw89_fw_element_id {
3781 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3782 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3783 RTW89_FW_ELEMENT_ID_BB_REG = 2,
3784 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3785 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3786 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3787 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3788 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3789 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3790 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3791 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3792 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3793 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3794 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3795 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3796 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3797 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3798 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3799 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3800 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3801
3802 RTW89_FW_ELEMENT_ID_NUM,
3803 };
3804
3805 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
3806 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3807 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3808 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3809 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3810 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3811 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3812 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3813
3814 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3815 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
3816 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3817 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3818
3819 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
3820 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3821 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3822 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3823 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3824 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3825 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
3826
3827 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3828 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3829 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3830 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3831 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3832 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3833 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
3834
3835 struct __rtw89_fw_txpwr_element {
3836 u8 rsvd0;
3837 u8 rsvd1;
3838 u8 rfe_type;
3839 u8 ent_sz;
3840 __le32 num_ents;
3841 u8 content[];
3842 } __packed;
3843
3844 enum rtw89_fw_txpwr_trk_type {
3845 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
3846 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
3847 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
3848 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
3849 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
3850 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
3851
3852 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
3853 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
3854 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
3855 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
3856 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3857 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3858
3859 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
3860 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
3861 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
3862 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
3863 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
3864 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
3865 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
3866 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
3867 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
3868 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
3869
3870 RTW89_FW_TXPWR_TRK_TYPE_NR,
3871 };
3872
3873 struct rtw89_fw_txpwr_track_cfg {
3874 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
3875 };
3876
3877 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
3878 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3879 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3880 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3881 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3882 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
3883 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3884 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3885 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3886 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3887 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
3888 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3889 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3890 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3891 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3892 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3893 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3894 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3895 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
3896
3897 struct rtw89_fw_element_hdr {
3898 __le32 id; /* enum rtw89_fw_element_id */
3899 __le32 size; /* exclude header size */
3900 u8 ver[4];
3901 __le32 rsvd0;
3902 __le32 rsvd1;
3903 __le32 rsvd2;
3904 union {
3905 struct {
3906 u8 priv[8];
3907 u8 contents[];
3908 } __packed common;
3909 struct {
3910 u8 idx;
3911 u8 rsvd[7];
3912 struct {
3913 __le32 addr;
3914 __le32 data;
3915 } __packed regs[];
3916 } __packed reg2;
3917 struct {
3918 u8 cv;
3919 u8 priv[7];
3920 u8 contents[];
3921 } __packed bbmcu;
3922 struct {
3923 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
3924 __le32 rsvd;
3925 s8 contents[][DELTA_SWINGIDX_SIZE];
3926 } __packed txpwr_trk;
3927 struct {
3928 u8 nr;
3929 u8 rsvd[3];
3930 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
3931 u8 rsvd1[3];
3932 __le16 offset[];
3933 } __packed rfk_log_fmt;
3934 struct __rtw89_fw_txpwr_element txpwr;
3935 } __packed u;
3936 } __packed;
3937
3938 struct fwcmd_hdr {
3939 __le32 hdr0;
3940 __le32 hdr1;
3941 };
3942
3943 union rtw89_compat_fw_hdr {
3944 struct rtw89_mfw_hdr mfw_hdr;
3945 struct rtw89_fw_hdr fw_hdr;
3946 };
3947
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)3948 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3949 {
3950 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3951
3952 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3953 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3954 else
3955 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3956 }
3957
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)3958 static inline void rtw89_fw_get_filename(char *buf, size_t size,
3959 const char *fw_basename, int fw_format)
3960 {
3961 if (fw_format <= 0)
3962 snprintf(buf, size, "%s.bin", fw_basename);
3963 else
3964 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3965 }
3966
3967 #define RTW89_H2C_RF_PAGE_SIZE 500
3968 #define RTW89_H2C_RF_PAGE_NUM 3
3969 struct rtw89_fw_h2c_rf_reg_info {
3970 enum rtw89_rf_path rf_path;
3971 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3972 u16 curr_idx;
3973 };
3974
3975 #define H2C_SEC_CAM_LEN 24
3976
3977 #define H2C_HEADER_LEN 8
3978 #define H2C_HDR_CAT GENMASK(1, 0)
3979 #define H2C_HDR_CLASS GENMASK(7, 2)
3980 #define H2C_HDR_FUNC GENMASK(15, 8)
3981 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
3982 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
3983 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
3984 #define H2C_HDR_REC_ACK BIT(14)
3985 #define H2C_HDR_DONE_ACK BIT(15)
3986
3987 #define FWCMD_TYPE_H2C 0
3988
3989 #define H2C_CAT_TEST 0x0
3990
3991 /* CLASS 5 - FW STATUS TEST */
3992 #define H2C_CL_FW_STATUS_TEST 0x5
3993 #define H2C_FUNC_CPU_EXCEPTION 0x1
3994
3995 #define H2C_CAT_MAC 0x1
3996
3997 /* CLASS 0 - FW INFO */
3998 #define H2C_CL_FW_INFO 0x0
3999 #define H2C_FUNC_LOG_CFG 0x0
4000 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
4001
4002 /* CLASS 1 - WOW */
4003 #define H2C_CL_MAC_WOW 0x1
4004 enum rtw89_wow_h2c_func {
4005 H2C_FUNC_KEEP_ALIVE = 0x0,
4006 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4007 H2C_FUNC_WOW_GLOBAL = 0x2,
4008 H2C_FUNC_GTK_OFLD = 0x3,
4009 H2C_FUNC_ARP_OFLD = 0x4,
4010 H2C_FUNC_NLO = 0x7,
4011 H2C_FUNC_WAKEUP_CTRL = 0x8,
4012 H2C_FUNC_WOW_CAM_UPD = 0xC,
4013 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4014
4015 NUM_OF_RTW89_WOW_H2C_FUNC,
4016 };
4017
4018 #define RTW89_WOW_WAIT_COND(tag, func) \
4019 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4020
4021 #define RTW89_WOW_WAIT_COND_AOAC \
4022 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4023
4024 /* CLASS 2 - PS */
4025 #define H2C_CL_MAC_PS 0x2
4026 enum rtw89_ps_h2c_func {
4027 H2C_FUNC_MAC_LPS_PARM = 0x0,
4028 H2C_FUNC_P2P_ACT = 0x1,
4029 H2C_FUNC_IPS_CFG = 0x3,
4030
4031 NUM_OF_RTW89_PS_H2C_FUNC,
4032 };
4033
4034 #define RTW89_PS_WAIT_COND(tag, func) \
4035 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4036
4037 #define RTW89_PS_WAIT_COND_IPS_CFG \
4038 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4039
4040 /* CLASS 3 - FW download */
4041 #define H2C_CL_MAC_FWDL 0x3
4042 #define H2C_FUNC_MAC_FWHDR_DL 0x0
4043
4044 /* CLASS 5 - Frame Exchange */
4045 #define H2C_CL_MAC_FR_EXCHG 0x5
4046 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4047 #define H2C_FUNC_MAC_BCN_UPD 0x5
4048 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4049 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4050 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4051 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4052 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4053
4054 /* CLASS 6 - Address CAM */
4055 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4056 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4057
4058 /* CLASS 8 - Media Status Report */
4059 #define H2C_CL_MAC_MEDIA_RPT 0x8
4060 #define H2C_FUNC_MAC_JOININFO 0x0
4061 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4062 #define H2C_FUNC_NOTIFY_DBCC 0x5
4063
4064 /* CLASS 9 - FW offload */
4065 #define H2C_CL_MAC_FW_OFLD 0x9
4066 enum rtw89_fw_ofld_h2c_func {
4067 H2C_FUNC_PACKET_OFLD = 0x1,
4068 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4069 H2C_FUNC_USR_EDCA = 0xF,
4070 H2C_FUNC_TSF32_TOGL = 0x10,
4071 H2C_FUNC_OFLD_CFG = 0x14,
4072 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4073 H2C_FUNC_SCANOFLD = 0x17,
4074 H2C_FUNC_PKT_DROP = 0x1b,
4075 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4076 H2C_FUNC_OFLD_RSSI = 0x1f,
4077 H2C_FUNC_OFLD_TP = 0x20,
4078 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4079 H2C_FUNC_SCANOFLD_BE = 0x2c,
4080
4081 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4082 };
4083
4084 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4085 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4086
4087 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4088 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4089 H2C_FUNC_PACKET_OFLD)
4090
4091 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4092
4093 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4094 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4095 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4096 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4097
4098
4099 /* CLASS 10 - Security CAM */
4100 #define H2C_CL_MAC_SEC_CAM 0xa
4101 #define H2C_FUNC_MAC_SEC_UPD 0x1
4102
4103 /* CLASS 12 - BA CAM */
4104 #define H2C_CL_BA_CAM 0xc
4105 #define H2C_FUNC_MAC_BA_CAM 0x0
4106 #define H2C_FUNC_MAC_BA_CAM_V1 0x1
4107 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4108
4109 /* CLASS 14 - MCC */
4110 #define H2C_CL_MCC 0xe
4111 enum rtw89_mcc_h2c_func {
4112 H2C_FUNC_ADD_MCC = 0x0,
4113 H2C_FUNC_START_MCC = 0x1,
4114 H2C_FUNC_STOP_MCC = 0x2,
4115 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4116 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4117 H2C_FUNC_MCC_REQ_TSF = 0x5,
4118 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4119 H2C_FUNC_MCC_SYNC = 0x7,
4120 H2C_FUNC_MCC_SET_DURATION = 0x8,
4121
4122 NUM_OF_RTW89_MCC_H2C_FUNC,
4123 };
4124
4125 #define RTW89_MCC_WAIT_COND(group, func) \
4126 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4127
4128 /* CLASS 24 - MRC */
4129 #define H2C_CL_MRC 0x18
4130 enum rtw89_mrc_h2c_func {
4131 H2C_FUNC_MRC_REQ_TSF = 0x0,
4132 H2C_FUNC_ADD_MRC = 0x1,
4133 H2C_FUNC_START_MRC = 0x2,
4134 H2C_FUNC_DEL_MRC = 0x3,
4135 H2C_FUNC_MRC_SYNC = 0x4,
4136 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4137 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4138
4139 NUM_OF_RTW89_MRC_H2C_FUNC,
4140 };
4141
4142 /* can consider MRC's sch_idx as MCC's group */
4143 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4144 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4145
4146 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4147 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4148
4149 #define H2C_CAT_OUTSRC 0x2
4150
4151 #define H2C_CL_OUTSRC_RA 0x1
4152 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4153
4154 #define H2C_CL_OUTSRC_DM 0x2
4155 #define H2C_FUNC_FW_LPS_CH_INFO 0xb
4156
4157 #define H2C_CL_OUTSRC_RF_REG_A 0x8
4158 #define H2C_CL_OUTSRC_RF_REG_B 0x9
4159 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4160 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4161 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4162
4163 enum rtw89_rfk_offload_h2c_func {
4164 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4165 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4166 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4167 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4168 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4169 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4170 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4171 };
4172
4173 struct rtw89_fw_h2c_rf_get_mccch {
4174 __le32 ch_0;
4175 __le32 ch_1;
4176 __le32 band_0;
4177 __le32 band_1;
4178 __le32 current_channel;
4179 __le32 current_band_type;
4180 } __packed;
4181
4182 #define NUM_OF_RTW89_FW_RFK_PATH 2
4183 #define NUM_OF_RTW89_FW_RFK_TBL 3
4184
4185 struct rtw89_fw_h2c_rfk_pre_info_common {
4186 struct {
4187 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4188 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4189 } __packed dbcc;
4190
4191 __le32 mlo_mode;
4192 struct {
4193 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4194 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4195 } __packed tbl;
4196
4197 __le32 phy_idx;
4198 } __packed;
4199
4200 struct rtw89_fw_h2c_rfk_pre_info_v0 {
4201 struct rtw89_fw_h2c_rfk_pre_info_common common;
4202
4203 __le32 cur_band;
4204 __le32 cur_bw;
4205 __le32 cur_center_ch;
4206
4207 __le32 ktbl_sel0;
4208 __le32 ktbl_sel1;
4209 __le32 rfmod0;
4210 __le32 rfmod1;
4211
4212 __le32 mlo_1_1;
4213 __le32 rfe_type;
4214 __le32 drv_mode;
4215
4216 struct {
4217 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4218 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4219 } __packed mlo;
4220 } __packed;
4221
4222 struct rtw89_fw_h2c_rfk_pre_info {
4223 struct rtw89_fw_h2c_rfk_pre_info_common common;
4224 __le32 mlo_1_1;
4225 } __packed;
4226
4227 struct rtw89_h2c_rf_tssi {
4228 __le16 len;
4229 u8 phy;
4230 u8 ch;
4231 u8 bw;
4232 u8 band;
4233 u8 hwtx_en;
4234 u8 cv;
4235 s8 curr_tssi_cck_de[2];
4236 s8 curr_tssi_cck_de_20m[2];
4237 s8 curr_tssi_cck_de_40m[2];
4238 s8 curr_tssi_efuse_cck_de[2];
4239 s8 curr_tssi_ofdm_de[2];
4240 s8 curr_tssi_ofdm_de_20m[2];
4241 s8 curr_tssi_ofdm_de_40m[2];
4242 s8 curr_tssi_ofdm_de_80m[2];
4243 s8 curr_tssi_ofdm_de_160m[2];
4244 s8 curr_tssi_ofdm_de_320m[2];
4245 s8 curr_tssi_efuse_ofdm_de[2];
4246 s8 curr_tssi_ofdm_de_diff_20m[2];
4247 s8 curr_tssi_ofdm_de_diff_80m[2];
4248 s8 curr_tssi_ofdm_de_diff_160m[2];
4249 s8 curr_tssi_ofdm_de_diff_320m[2];
4250 s8 curr_tssi_trim_de[2];
4251 u8 pg_thermal[2];
4252 u8 ftable[2][128];
4253 u8 tssi_mode;
4254 } __packed;
4255
4256 struct rtw89_h2c_rf_iqk {
4257 __le32 phy_idx;
4258 __le32 dbcc;
4259 } __packed;
4260
4261 struct rtw89_h2c_rf_dpk {
4262 u8 len;
4263 u8 phy;
4264 u8 dpk_enable;
4265 u8 kpath;
4266 u8 cur_band;
4267 u8 cur_bw;
4268 u8 cur_ch;
4269 u8 dpk_dbg_en;
4270 } __packed;
4271
4272 struct rtw89_h2c_rf_txgapk {
4273 u8 len;
4274 u8 ktype;
4275 u8 phy;
4276 u8 kpath;
4277 u8 band;
4278 u8 bw;
4279 u8 ch;
4280 u8 cv;
4281 } __packed;
4282
4283 struct rtw89_h2c_rf_dack {
4284 __le32 len;
4285 __le32 phy;
4286 __le32 type;
4287 } __packed;
4288
4289 struct rtw89_h2c_rf_rxdck {
4290 u8 len;
4291 u8 phy;
4292 u8 is_afe;
4293 u8 kpath;
4294 u8 cur_band;
4295 u8 cur_bw;
4296 u8 cur_ch;
4297 u8 rxdck_dbg_en;
4298 } __packed;
4299
4300 enum rtw89_rf_log_type {
4301 RTW89_RF_RUN_LOG = 0,
4302 RTW89_RF_RPT_LOG = 1,
4303 };
4304
4305 struct rtw89_c2h_rf_log_hdr {
4306 u8 type; /* enum rtw89_rf_log_type */
4307 __le16 len;
4308 u8 content[];
4309 } __packed;
4310
4311 struct rtw89_c2h_rf_run_log {
4312 __le32 fmt_idx;
4313 __le32 arg[4];
4314 } __packed;
4315
4316 struct rtw89_c2h_rf_dpk_rpt_log {
4317 u8 ver;
4318 u8 idx[2];
4319 u8 band[2];
4320 u8 bw[2];
4321 u8 ch[2];
4322 u8 path_ok[2];
4323 u8 txagc[2];
4324 u8 ther[2];
4325 u8 gs[2];
4326 u8 dc_i[4];
4327 u8 dc_q[4];
4328 u8 corr_val[2];
4329 u8 corr_idx[2];
4330 u8 is_timeout[2];
4331 u8 rxbb_ov[2];
4332 u8 rsvd;
4333 } __packed;
4334
4335 struct rtw89_c2h_rf_dack_rpt_log {
4336 u8 fwdack_ver;
4337 u8 fwdack_rpt_ver;
4338 u8 msbk_d[2][2][16];
4339 u8 dadck_d[2][2];
4340 u8 cdack_d[2][2][2];
4341 __le16 addck2_d[2][2][2];
4342 u8 adgaink_d[2][2];
4343 __le16 biask_d[2][2];
4344 u8 addck_timeout;
4345 u8 cdack_timeout;
4346 u8 dadck_timeout;
4347 u8 msbk_timeout;
4348 u8 adgaink_timeout;
4349 u8 dack_fail;
4350 } __packed;
4351
4352 struct rtw89_c2h_rf_rxdck_rpt_log {
4353 u8 ver;
4354 u8 band[2];
4355 u8 bw[2];
4356 u8 ch[2];
4357 u8 timeout[2];
4358 } __packed;
4359
4360 struct rtw89_c2h_rf_txgapk_rpt_log {
4361 __le32 r0x8010[2];
4362 __le32 chk_cnt;
4363 u8 track_d[2][17];
4364 u8 power_d[2][17];
4365 u8 is_txgapk_ok;
4366 u8 chk_id;
4367 u8 ver;
4368 u8 rsv1;
4369 } __packed;
4370
4371 struct rtw89_c2h_rfk_report {
4372 struct rtw89_c2h_hdr hdr;
4373 u8 state; /* enum rtw89_rfk_report_state */
4374 u8 version;
4375 } __packed;
4376
4377 #define RTW89_FW_RSVD_PLE_SIZE 0x800
4378
4379 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
4380 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4381 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4382
4383 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4384 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4385
4386 #define FWDL_WAIT_CNT 400000
4387
4388 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4389 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4390 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4391 const struct firmware *
4392 rtw89_early_fw_feature_recognize(struct device *device,
4393 const struct rtw89_chip_info *chip,
4394 struct rtw89_fw_info *early_fw,
4395 int *used_fw_format);
4396 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4397 bool include_bb);
4398 void rtw89_load_firmware_work(struct work_struct *work);
4399 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4400 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4401 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4402 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4403 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4404 u8 type, u8 cat, u8 class, u8 func,
4405 bool rack, bool dack, u32 len);
4406 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4407 struct rtw89_vif *rtwvif,
4408 struct rtw89_sta *rtwsta);
4409 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4410 struct rtw89_vif *rtwvif,
4411 struct rtw89_sta *rtwsta);
4412 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4413 struct rtw89_vif *rtwvif,
4414 struct rtw89_sta *rtwsta);
4415 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4416 struct ieee80211_vif *vif,
4417 struct ieee80211_sta *sta);
4418 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4419 struct ieee80211_vif *vif,
4420 struct ieee80211_sta *sta);
4421 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4422 struct ieee80211_vif *vif,
4423 struct ieee80211_sta *sta);
4424 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4425 struct rtw89_sta *rtwsta);
4426 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4427 struct rtw89_sta *rtwsta);
4428 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4429 struct rtw89_vif *rtwvif);
4430 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4431 struct rtw89_vif *rtwvif);
4432 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
4433 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
4434 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4435 struct rtw89_vif *rtwvif,
4436 struct rtw89_sta *rtwsta);
4437 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4438 struct rtw89_vif *rtwvif,
4439 struct rtw89_sta *rtwsta);
4440 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4441 void rtw89_fw_c2h_work(struct work_struct *work);
4442 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4443 struct rtw89_vif *rtwvif,
4444 struct rtw89_sta *rtwsta,
4445 enum rtw89_upd_mode upd_mode);
4446 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4447 struct rtw89_sta *rtwsta, bool dis_conn);
4448 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4449 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4450 bool pause);
4451 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4452 u8 ac, u32 val);
4453 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4454 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4455 struct ieee80211_vif *vif,
4456 bool connect);
4457 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4458 struct rtw89_rx_phy_ppdu *phy_ppdu);
4459 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4460 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4461 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4462 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4463 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4464 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4465 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4466 int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
4467 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
4468 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4469 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4470 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4471 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4472 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4473 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4474 struct sk_buff *skb_ofld);
4475 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int ch_num,
4476 struct list_head *chan_list);
4477 int rtw89_fw_h2c_scan_list_offload_be(struct rtw89_dev *rtwdev, int ch_num,
4478 struct list_head *chan_list);
4479 int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
4480 struct rtw89_scan_option *opt,
4481 struct rtw89_vif *vif,
4482 bool wowlan);
4483 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4484 struct rtw89_scan_option *opt,
4485 struct rtw89_vif *vif,
4486 bool wowlan);
4487 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4488 struct rtw89_fw_h2c_rf_reg_info *info,
4489 u16 len, u8 page);
4490 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4491 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4492 enum rtw89_phy_idx phy_idx);
4493 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4494 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
4495 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4496 const struct rtw89_chan *chan);
4497 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4498 const struct rtw89_chan *chan);
4499 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4500 const struct rtw89_chan *chan);
4501 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4502 const struct rtw89_chan *chan);
4503 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4504 const struct rtw89_chan *chan);
4505 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4506 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4507 bool rack, bool dack);
4508 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4509 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4510 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4511 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4512 u8 macid);
4513 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4514 struct rtw89_vif *rtwvif, bool notify_fw);
4515 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4516 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4517 bool valid, struct ieee80211_ampdu_params *params);
4518 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4519 bool valid, struct ieee80211_ampdu_params *params);
4520 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4521 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4522 u8 offset, u8 mac_idx);
4523
4524 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4525 struct rtw89_lps_parm *lps_param);
4526 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev,
4527 struct rtw89_vif *rtwvif);
4528 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4529 bool enable);
4530 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
4531 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
4532 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
4533 struct rtw89_mac_h2c_info *h2c_info,
4534 struct rtw89_mac_c2h_info *c2h_info);
4535 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
4536 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
4537 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4538 struct ieee80211_scan_request *req);
4539 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4540 bool aborted);
4541 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4542 bool enable);
4543 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
4544 int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4545 struct rtw89_vif *rtwvif, bool connected);
4546 int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4547 struct rtw89_vif *rtwvif);
4548 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4549 struct rtw89_vif *rtwvif, bool connected);
4550 int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4551 struct rtw89_vif *rtwvif);
4552 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
4553 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
4554 const struct rtw89_pkt_drop_params *params);
4555 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4556 struct ieee80211_p2p_noa_desc *desc,
4557 u8 act, u8 noa_id);
4558 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4559 bool en);
4560 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4561 bool enable);
4562 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4563 struct rtw89_vif *rtwvif, bool enable);
4564 int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4565 bool enable);
4566 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4567 bool enable);
4568 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
4569 struct rtw89_vif *rtwvif, bool enable);
4570 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
4571 struct rtw89_vif *rtwvif, bool enable);
4572 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4573 bool enable);
4574 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4575 struct rtw89_vif *rtwvif, bool enable);
4576 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
4577 struct rtw89_wow_cam_info *cam_info);
4578 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
4579 struct rtw89_vif *rtwvif,
4580 bool enable);
4581 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
4582 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
4583 const struct rtw89_fw_mcc_add_req *p);
4584 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
4585 const struct rtw89_fw_mcc_start_req *p);
4586 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4587 bool prev_groups);
4588 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
4589 bool prev_groups);
4590 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
4591 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
4592 const struct rtw89_fw_mcc_tsf_req *req,
4593 struct rtw89_mac_mcc_tsf_rpt *rpt);
4594 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4595 u8 *bitmap);
4596 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
4597 u8 target, u8 offset);
4598 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
4599 const struct rtw89_fw_mcc_duration *p);
4600 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
4601 const struct rtw89_fw_mrc_add_arg *arg);
4602 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
4603 const struct rtw89_fw_mrc_start_arg *arg);
4604 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
4605 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
4606 const struct rtw89_fw_mrc_req_tsf_arg *arg,
4607 struct rtw89_mac_mrc_tsf_rpt *rpt);
4608 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
4609 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
4610 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
4611 const struct rtw89_fw_mrc_sync_arg *arg);
4612 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
4613 const struct rtw89_fw_mrc_upd_duration_arg *arg);
4614
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)4615 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
4616 {
4617 const struct rtw89_chip_info *chip = rtwdev->chip;
4618
4619 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4620 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
4621 }
4622
rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4623 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4624 struct rtw89_vif *rtwvif,
4625 struct rtw89_sta *rtwsta)
4626 {
4627 const struct rtw89_chip_info *chip = rtwdev->chip;
4628
4629 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta);
4630 }
4631
rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4632 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
4633 struct rtw89_vif *rtwvif,
4634 struct rtw89_sta *rtwsta)
4635 {
4636 const struct rtw89_chip_info *chip = rtwdev->chip;
4637
4638 if (chip->ops->h2c_default_dmac_tbl)
4639 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta);
4640
4641 return 0;
4642 }
4643
rtw89_chip_h2c_update_beacon(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4644 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
4645 struct rtw89_vif *rtwvif)
4646 {
4647 const struct rtw89_chip_info *chip = rtwdev->chip;
4648
4649 return chip->ops->h2c_update_beacon(rtwdev, rtwvif);
4650 }
4651
rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4652 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4653 struct ieee80211_vif *vif,
4654 struct ieee80211_sta *sta)
4655 {
4656 const struct rtw89_chip_info *chip = rtwdev->chip;
4657
4658 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, vif, sta);
4659 }
4660
rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4661 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
4662 struct ieee80211_vif *vif,
4663 struct ieee80211_sta *sta)
4664 {
4665 const struct rtw89_chip_info *chip = rtwdev->chip;
4666
4667 if (chip->ops->h2c_ampdu_cmac_tbl)
4668 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, vif, sta);
4669
4670 return 0;
4671 }
4672
4673 static inline
rtw89_chip_h2c_ba_cam(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool valid,struct ieee80211_ampdu_params * params)4674 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4675 bool valid, struct ieee80211_ampdu_params *params)
4676 {
4677 const struct rtw89_chip_info *chip = rtwdev->chip;
4678
4679 return chip->ops->h2c_ba_cam(rtwdev, rtwsta, valid, params);
4680 }
4681
4682 /* must consider compatibility; don't insert new in the mid */
4683 struct rtw89_fw_txpwr_byrate_entry {
4684 u8 band;
4685 u8 nss;
4686 u8 rs;
4687 u8 shf;
4688 u8 len;
4689 __le32 data;
4690 u8 bw;
4691 u8 ofdma;
4692 } __packed;
4693
4694 /* must consider compatibility; don't insert new in the mid */
4695 struct rtw89_fw_txpwr_lmt_2ghz_entry {
4696 u8 bw;
4697 u8 nt;
4698 u8 rs;
4699 u8 bf;
4700 u8 regd;
4701 u8 ch_idx;
4702 s8 v;
4703 } __packed;
4704
4705 /* must consider compatibility; don't insert new in the mid */
4706 struct rtw89_fw_txpwr_lmt_5ghz_entry {
4707 u8 bw;
4708 u8 nt;
4709 u8 rs;
4710 u8 bf;
4711 u8 regd;
4712 u8 ch_idx;
4713 s8 v;
4714 } __packed;
4715
4716 /* must consider compatibility; don't insert new in the mid */
4717 struct rtw89_fw_txpwr_lmt_6ghz_entry {
4718 u8 bw;
4719 u8 nt;
4720 u8 rs;
4721 u8 bf;
4722 u8 regd;
4723 u8 reg_6ghz_power;
4724 u8 ch_idx;
4725 s8 v;
4726 } __packed;
4727
4728 /* must consider compatibility; don't insert new in the mid */
4729 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
4730 u8 ru;
4731 u8 nt;
4732 u8 regd;
4733 u8 ch_idx;
4734 s8 v;
4735 } __packed;
4736
4737 /* must consider compatibility; don't insert new in the mid */
4738 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
4739 u8 ru;
4740 u8 nt;
4741 u8 regd;
4742 u8 ch_idx;
4743 s8 v;
4744 } __packed;
4745
4746 /* must consider compatibility; don't insert new in the mid */
4747 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
4748 u8 ru;
4749 u8 nt;
4750 u8 regd;
4751 u8 reg_6ghz_power;
4752 u8 ch_idx;
4753 s8 v;
4754 } __packed;
4755
4756 /* must consider compatibility; don't insert new in the mid */
4757 struct rtw89_fw_tx_shape_lmt_entry {
4758 u8 band;
4759 u8 tx_shape_rs;
4760 u8 regd;
4761 u8 v;
4762 } __packed;
4763
4764 /* must consider compatibility; don't insert new in the mid */
4765 struct rtw89_fw_tx_shape_lmt_ru_entry {
4766 u8 band;
4767 u8 regd;
4768 u8 v;
4769 } __packed;
4770
4771 const struct rtw89_rfe_parms *
4772 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
4773 const struct rtw89_rfe_parms *init);
4774
4775 enum rtw89_wow_wakeup_ver {
4776 RTW89_WOW_REASON_V0,
4777 RTW89_WOW_REASON_V1,
4778 RTW89_WOW_REASON_NUM,
4779 };
4780
4781 #endif
4782