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Searched refs:UVD_CGC_UDEC_STATUS__CM_DCLK_MASK (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h275 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 macro
H A Duvd_4_2_sh_mask.h275 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 macro
H A Duvd_4_0_sh_mask.h208 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L macro
H A Duvd_5_0_sh_mask.h299 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 macro
H A Duvd_6_0_sh_mask.h301 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2045 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1997 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3716 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2775 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3449 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3759 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK … macro
H A Dvcn_4_0_0_sh_mask.h3893 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK … macro
H A Dvcn_4_0_3_sh_mask.h3928 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK … macro