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Searched refs:UVD_MPC_SET_MUXB0__VARB_1__SHIFT (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h617 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
H A Duvd_3_1_sh_mask.h496 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 macro
H A Duvd_4_2_sh_mask.h500 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 macro
H A Duvd_4_0_sh_mask.h513 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x00000006 macro
H A Duvd_5_0_sh_mask.h532 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 macro
H A Duvd_6_0_sh_mask.h534 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1124 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2865 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2630 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h2857 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3938 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h4055 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4188 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4231 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c930 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v4_0_5_start_dpg_mode()
1069 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c829 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v4_0_3_start_dpg_mode()
1155 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v4_0_3_start()
H A Dvcn_v1_0.c878 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v1_0_start_spg_mode()
1061 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_0.c895 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v2_0_start_dpg_mode()
1028 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v2_0_start()
H A Dvcn_v4_0.c1015 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v4_0_start_dpg_mode()
1157 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v4_0_start()
H A Dvcn_v2_5.c924 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v2_5_start_dpg_mode()
1078 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v2_5_start()
H A Dvcn_v3_0.c1044 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v3_0_start_dpg_mode()
1208 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | in vcn_v3_0_start()