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Searched refs:asyh (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dhead.c101 if (asyh->base.depth > asyh->or.bpc * 3) in nv50_head_atomic_check_dither()
169 asyh->view.oW -= (asyh->view.oW >> 4) + 32; in nv50_head_atomic_check_view()
183 asyh->view.oW = min(asyh->view.iW, asyh->view.oW); in nv50_head_atomic_check_view()
184 asyh->view.oH = min(asyh->view.iH, asyh->view.oH); in nv50_head_atomic_check_view()
202 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) { in nv50_head_atomic_check_view()
250 if (asyh->wndw.olut != asyh->wndw.mask) in nv50_head_atomic_check_lut()
272 asyh->olut.buffer = !asyh->olut.buffer; in nv50_head_atomic_check_lut()
434 asyh->set.olut = asyh->olut.visible; in nv50_head_atomic_check()
435 asyh->set.core = asyh->core.visible; in nv50_head_atomic_check()
436 asyh->set.curs = asyh->curs.visible; in nv50_head_atomic_check()
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H A Dhead507d.c241 asyh->set.curs = asyh->curs.visible; in head507d_core_set()
242 asyh->set.olut = asyh->olut.handle != 0; in head507d_core_set()
250 if ((asyh->core.visible = (asyh->base.cpp != 0))) { in head507d_core_calc()
251 asyh->core.x = asyh->base.x; in head507d_core_calc()
252 asyh->core.y = asyh->base.y; in head507d_core_calc()
253 asyh->core.w = asyh->base.w; in head507d_core_calc()
254 asyh->core.h = asyh->base.h; in head507d_core_calc()
257 (asyh->core.visible = asyh->curs.visible)) { in head507d_core_calc()
265 asyh->core.w = asyh->state.mode.hdisplay; in head507d_core_calc()
266 asyh->core.h = asyh->state.mode.vdisplay; in head507d_core_calc()
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H A Dhead907d.c37 head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh) in head907d_or() argument
103 if (asyh->ovly.cpp) { in head907d_ovly()
104 switch (asyh->ovly.cpp) { in head907d_ovly()
132 if (asyh->base.cpp) { in head907d_base()
133 switch (asyh->base.cpp) { in head907d_base()
189 HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); in head907d_curs_set()
223 NVVAL(NV907D, HEAD_SET_SIZE, WIDTH, asyh->core.w) | in head907d_core_set()
224 NVVAL(NV907D, HEAD_SET_SIZE, HEIGHT, asyh->core.h), in head907d_core_set()
229 NVVAL(NV907D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) | in head907d_core_set()
313 asyh->olut.load = head907d_olut_load; in head907d_olut()
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H A Dheadc37d.c31 headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh) in headc37d_or() argument
41 switch (asyh->or.depth) { in headc37d_or()
47 depth = asyh->or.depth; in headc37d_or()
86 headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) in headc37d_dither() argument
155 struct nv50_head_atom *asyh) in headc37d_curs_format() argument
157 asyh->curs.format = asyw->image.format; in headc37d_curs_format()
190 HEAD_SET_OFFSET_OUTPUT_LUT(i), asyh->olut.offset >> 8, in headc37d_olut_set()
191 HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), asyh->olut.handle); in headc37d_olut_set()
205 asyh->olut.load = head907d_olut_load; in headc37d_olut()
213 struct nv50_head_mode *m = &asyh->mode; in headc37d_mode()
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H A Dhead827d.c61 NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in head827d_curs_set()
67 HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); in head827d_curs_set()
84 NVVAL(NV827D, HEAD_SET_OFFSET, ORIGIN, asyh->core.offset >> 8)); in head827d_core_set()
87 NVVAL(NV827D, HEAD_SET_SIZE, WIDTH, asyh->core.w) | in head827d_core_set()
88 NVVAL(NV827D, HEAD_SET_SIZE, HEIGHT, asyh->core.h), in head827d_core_set()
92 NVVAL(NV827D, HEAD_SET_STORAGE, PITCH, asyh->core.pitch >> 8) | in head827d_core_set()
93 NVVAL(NV827D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) | in head827d_core_set()
97 NVVAL(NV827D, HEAD_SET_PARAMS, FORMAT, asyh->core.format) | in head827d_core_set()
105 NVVAL(NV827D, HEAD_SET_VIEWPORT_POINT_IN, X, asyh->core.x) | in head827d_core_set()
106 NVVAL(NV827D, HEAD_SET_VIEWPORT_POINT_IN, Y, asyh->core.y)); in head827d_core_set()
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H A Dhead917d.c31 head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) in head917d_dither() argument
41 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | in head917d_dither()
42 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | in head917d_dither()
43 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head917d_dither()
49 head917d_base(struct nv50_head *head, struct nv50_head_atom *asyh) in head917d_base() argument
56 if (asyh->base.cpp) { in head917d_base()
57 switch (asyh->base.cpp) { in head917d_base()
78 head917d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) in head917d_curs_set() argument
91 NVVAL(NV917D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | in head917d_curs_set()
96 HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); in head917d_curs_set()
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H A Dheadc57d.c44 headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh) in headc57d_or() argument
54 switch (asyh->or.depth) { in headc57d_or()
60 depth = asyh->or.depth; in headc57d_or()
123 NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) | in headc57d_olut_set()
124 NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, SIZE, asyh->olut.size), in headc57d_olut_set()
127 HEAD_SET_CONTEXT_DMA_OLUT(i), asyh->olut.handle, in headc57d_olut_set()
128 HEAD_SET_OFFSET_OLUT(i), asyh->olut.offset >> 8); in headc57d_olut_set()
191 asyh->olut.mode = NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10; in headc57d_olut()
195 asyh->olut.load = headc57d_olut_load_8; in headc57d_olut()
197 asyh->olut.load = headc57d_olut_load; in headc57d_olut()
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H A Dcurs507a.c83 if (asyh->curs.handle != handle || asyh->curs.offset != offset) { in curs507a_prepare()
84 asyh->curs.handle = handle; in curs507a_prepare()
85 asyh->curs.offset = offset; in curs507a_prepare()
86 asyh->set.curs = asyh->curs.visible; in curs507a_prepare()
92 struct nv50_head_atom *asyh) in curs507a_release() argument
94 asyh->curs.visible = false; in curs507a_release()
99 struct nv50_head_atom *asyh) in curs507a_acquire() argument
110 asyh->curs.visible = asyw->state.visible; in curs507a_acquire()
111 if (ret || !asyh->curs.visible) in curs507a_acquire()
136 ret = head->func->curs_layout(head, asyw, asyh); in curs507a_acquire()
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H A Dcrc.c251 if (!asyh->clr.crc) in nv50_crc_atomic_stop_reporting()
284 if (!asyh->set.crc) in nv50_crc_atomic_init_notifier_contexts()
308 if (!asyh->clr.crc) in nv50_crc_atomic_release_notifier_contexts()
331 if (!asyh->set.crc) in nv50_crc_atomic_start_reporting()
359 asyh->set.crc = false; in nv50_crc_atomic_check_head()
360 asyh->clr.crc = false; in nv50_crc_atomic_check_head()
366 asyh->set.crc = asyh->crc.src && asyh->state.active; in nv50_crc_atomic_check_head()
371 if (asyh->clr.crc && asyh->set.crc) in nv50_crc_atomic_check_head()
374 asyh->set.crc = false; in nv50_crc_atomic_check_head()
375 asyh->clr.crc = false; in nv50_crc_atomic_check_head()
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H A Dbase507c.c226 struct nv50_head_atom *asyh) in base507c_release() argument
228 asyh->base.cpp = 0; in base507c_release()
233 struct nv50_head_atom *asyh) in base507c_acquire() argument
247 asyh->state.color_mgmt_changed = true; in base507c_acquire()
250 asyh->base.depth = fb->format->depth; in base507c_acquire()
251 asyh->base.cpp = fb->format->cpp[0]; in base507c_acquire()
252 asyh->base.x = asyw->state.src.x1 >> 16; in base507c_acquire()
254 asyh->base.w = asyw->state.fb->width; in base507c_acquire()
255 asyh->base.h = asyw->state.fb->height; in base507c_acquire()
261 if (!asyh->base.depth) in base507c_acquire()
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H A Dpior507d.c31 struct nv50_head_atom *asyh) in pior507d_ctrl() argument
36 if (asyh) { in pior507d_ctrl()
37 ctrl |= NVVAL(NV507D, PIOR_SET_CONTROL, HSYNC_POLARITY, asyh->or.nhsync); in pior507d_ctrl()
38 ctrl |= NVVAL(NV507D, PIOR_SET_CONTROL, VSYNC_POLARITY, asyh->or.nvsync); in pior507d_ctrl()
39 ctrl |= NVVAL(NV837D, PIOR_SET_CONTROL, PIXEL_DEPTH, asyh->or.depth); in pior507d_ctrl()
H A Dsor507d.c31 struct nv50_head_atom *asyh) in sor507d_ctrl() argument
36 if (asyh) { in sor507d_ctrl()
37 ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, HSYNC_POLARITY, asyh->or.nhsync); in sor507d_ctrl()
38 ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, VSYNC_POLARITY, asyh->or.nvsync); in sor507d_ctrl()
39 ctrl |= NVVAL(NV837D, SOR_SET_CONTROL, PIXEL_DEPTH, asyh->or.depth); in sor507d_ctrl()
H A Dwndw.c311 if (!asyh->state.async_flip) in nv50_wndw_atomic_check_acquire()
371 struct nv50_head_atom *asyh) in nv50_wndw_atomic_check_lut() argument
393 asyh->wndw.olut |= BIT(wndw->id); in nv50_wndw_atomic_check_lut()
432 asyh->state.async_flip = false; in nv50_wndw_atomic_check_lut()
457 if (IS_ERR(asyh)) in nv50_wndw_atomic_check()
458 return PTR_ERR(asyh); in nv50_wndw_atomic_check()
486 armw, asyw, asyh); in nv50_wndw_atomic_check()
490 asyh->wndw.mask |= BIT(wndw->id); in nv50_wndw_atomic_check()
539 struct nv50_head_atom *asyh; in nv50_wndw_prepare_fb() local
571 if (IS_ERR(asyh)) in nv50_wndw_prepare_fb()
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H A Ddac507d.c30 struct nv50_head_atom *asyh) in dac507d_ctrl() argument
36 if (asyh) { in dac507d_ctrl()
37 sync |= NVVAL(NV507D, DAC_SET_POLARITY, HSYNC, asyh->or.nhsync); in dac507d_ctrl()
38 sync |= NVVAL(NV507D, DAC_SET_POLARITY, VSYNC, asyh->or.nvsync); in dac507d_ctrl()
H A Ddisp.c380 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10); in nv50_outp_atomic_fix_depth()
388 asyh->or.bpc -= 2; in nv50_outp_atomic_fix_depth()
508 asyh->or.depth = 0; in nv50_dac_atomic_enable()
985 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4); in nv50_msto_atomic_check()
1003 asyh->dp.tu = slots; in nv50_msto_atomic_check()
1539 if (!asyh) { in nv50_sor_update()
1617 unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke; in nv50_sor_dp_watermark_sst()
2195 asyh->clr.mask, asyh->set.mask); in nv50_disp_atomic_commit_tail()
2202 if (asyh->clr.mask) { in nv50_disp_atomic_commit_tail()
2278 asyh->set.mask, asyh->clr.mask); in nv50_disp_atomic_commit_tail()
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H A Dovly507e.c95 struct nv50_head_atom *asyh) in ovly507e_release() argument
97 asyh->ovly.cpp = 0; in ovly507e_release()
102 struct nv50_head_atom *asyh) in ovly507e_acquire() argument
107 ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state, in ovly507e_acquire()
114 asyh->ovly.cpp = fb->format->cpp[0]; in ovly507e_acquire()
H A Dwndw.h50 struct nv50_head_atom *asyh);
52 struct nv50_head_atom *asyh);
53 void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
63 void (*ilut)(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyh, int size);
H A Dhead.h23 void nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh);
24 void nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh);
26 struct nv50_head_atom *asyh, bool flush);
H A Ddac907d.c30 struct nv50_head_atom *asyh) in dac907d_ctrl() argument
H A Dsorc37d.c30 struct nv50_head_atom *asyh) in sorc37d_ctrl() argument
H A Dsor907d.c33 struct nv50_head_atom *asyh) in sor907d_ctrl() argument
H A Dwndwc37e.c290 struct nv50_head_atom *asyh) in wndwc37e_release() argument
296 struct nv50_head_atom *asyh) in wndwc37e_acquire() argument
298 return drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state, in wndwc37e_acquire()
H A Dcrc.h114 struct nv50_head_atom *asyh, in nv50_crc_atomic_check_head() argument