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Searched refs:chip_types (Results 1 – 25 of 50) sorted by relevance

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/linux/drivers/irqchip/
H A Dirq-sunxi-nmi.c99 struct irq_chip_type *ct = gc->chip_types; in sunxi_sc_nmi_set_type()
184 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; in sunxi_sc_nmi_irq_init()
187 gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; in sunxi_sc_nmi_irq_init()
190 gc->chip_types[0].regs.ack = reg_offs->pend; in sunxi_sc_nmi_irq_init()
191 gc->chip_types[0].regs.mask = reg_offs->enable; in sunxi_sc_nmi_irq_init()
192 gc->chip_types[0].regs.type = reg_offs->ctrl; in sunxi_sc_nmi_irq_init()
194 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; in sunxi_sc_nmi_irq_init()
199 gc->chip_types[1].regs.ack = reg_offs->pend; in sunxi_sc_nmi_irq_init()
200 gc->chip_types[1].regs.mask = reg_offs->enable; in sunxi_sc_nmi_irq_init()
201 gc->chip_types[1].regs.type = reg_offs->ctrl; in sunxi_sc_nmi_irq_init()
[all …]
H A Dirq-pic32-evic.c269 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; in pic32_of_init()
270 gc->chip_types[0].handler = handle_fasteoi_irq; in pic32_of_init()
271 gc->chip_types[0].regs.ack = ifsclr; in pic32_of_init()
272 gc->chip_types[0].regs.mask = iec; in pic32_of_init()
273 gc->chip_types[0].chip.name = "evic-level"; in pic32_of_init()
274 gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; in pic32_of_init()
280 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; in pic32_of_init()
281 gc->chip_types[1].handler = handle_edge_irq; in pic32_of_init()
282 gc->chip_types[1].regs.ack = ifsclr; in pic32_of_init()
283 gc->chip_types[1].regs.mask = iec; in pic32_of_init()
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H A Dirq-imgpdc.c402 gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE; in pdc_intc_probe()
403 gc->chip_types[0].chip.irq_mask = perip_irq_mask; in pdc_intc_probe()
404 gc->chip_types[0].chip.irq_unmask = perip_irq_unmask; in pdc_intc_probe()
414 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH; in pdc_intc_probe()
415 gc->chip_types[0].handler = handle_edge_irq; in pdc_intc_probe()
416 gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR; in pdc_intc_probe()
417 gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE; in pdc_intc_probe()
427 gc->chip_types[1].type = IRQ_TYPE_LEVEL_MASK; in pdc_intc_probe()
428 gc->chip_types[1].handler = handle_level_irq; in pdc_intc_probe()
429 gc->chip_types[1].regs.ack = PDC_IRQ_CLEAR; in pdc_intc_probe()
[all …]
H A Dirq-tb10x.c146 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; in of_tb10x_init_irq()
147 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in of_tb10x_init_irq()
148 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in of_tb10x_init_irq()
149 gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type; in of_tb10x_init_irq()
150 gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE; in of_tb10x_init_irq()
152 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; in of_tb10x_init_irq()
153 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; in of_tb10x_init_irq()
154 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; in of_tb10x_init_irq()
155 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; in of_tb10x_init_irq()
156 gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type; in of_tb10x_init_irq()
[all …]
H A Dirq-zevio.c106 gc->chip_types[0].chip.irq_ack = zevio_irq_ack; in zevio_of_init()
107 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in zevio_of_init()
108 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in zevio_of_init()
109 gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE; in zevio_of_init()
110 gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE; in zevio_of_init()
111 gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE; in zevio_of_init()
112 gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET; in zevio_of_init()
H A Dirq-lan966x-oic.c176 gc->chip_types[0].regs.enable = chip_regs->reg_off_ena_set; in lan966x_oic_chip_init()
177 gc->chip_types[0].regs.disable = chip_regs->reg_off_ena_clr; in lan966x_oic_chip_init()
178 gc->chip_types[0].regs.ack = chip_regs->reg_off_sticky; in lan966x_oic_chip_init()
179 gc->chip_types[0].chip.irq_startup = lan966x_oic_irq_startup; in lan966x_oic_chip_init()
180 gc->chip_types[0].chip.irq_shutdown = lan966x_oic_irq_shutdown; in lan966x_oic_chip_init()
181 gc->chip_types[0].chip.irq_set_type = lan966x_oic_irq_set_type; in lan966x_oic_chip_init()
182 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in lan966x_oic_chip_init()
183 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in lan966x_oic_chip_init()
184 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in lan966x_oic_chip_init()
196 irq_reg_writel(gc, ~0U, gc->chip_types[0].regs.disable); in lan966x_oic_chip_exit()
[all …]
H A Dirq-orion.c89 gc->chip_types[0].regs.mask = ORION_IRQ_MASK; in orion_irq_init()
90 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in orion_irq_init()
91 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in orion_irq_init()
188 gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE; in orion_bridge_irq_init()
189 gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK; in orion_bridge_irq_init()
190 gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup; in orion_bridge_irq_init()
191 gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit; in orion_bridge_irq_init()
192 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in orion_bridge_irq_init()
193 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in orion_bridge_irq_init()
H A Dirq-atmel-aic.c257 gc->chip_types[0].regs.eoi = AT91_AIC_EOICR; in aic_of_init()
258 gc->chip_types[0].regs.enable = AT91_AIC_IECR; in aic_of_init()
259 gc->chip_types[0].regs.disable = AT91_AIC_IDCR; in aic_of_init()
260 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in aic_of_init()
261 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in aic_of_init()
262 gc->chip_types[0].chip.irq_retrigger = aic_retrigger; in aic_of_init()
263 gc->chip_types[0].chip.irq_set_type = aic_set_type; in aic_of_init()
264 gc->chip_types[0].chip.irq_suspend = aic_suspend; in aic_of_init()
265 gc->chip_types[0].chip.irq_resume = aic_resume; in aic_of_init()
266 gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown; in aic_of_init()
H A Dirq-mscc-ocelot.c158 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in vcoreiii_irq_init()
159 gc->chip_types[0].regs.ack = p->reg_off_sticky; in vcoreiii_irq_init()
161 gc->chip_types[0].regs.mask = p->reg_off_ena_clr; in vcoreiii_irq_init()
162 gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask; in vcoreiii_irq_init()
163 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in vcoreiii_irq_init()
165 gc->chip_types[0].regs.enable = p->reg_off_ena_set; in vcoreiii_irq_init()
166 gc->chip_types[0].regs.disable = p->reg_off_ena_clr; in vcoreiii_irq_init()
167 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in vcoreiii_irq_init()
168 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in vcoreiii_irq_init()
H A Dirq-al-fic.c58 gc->chip_types->handler = handler; in al_fic_set_trigger()
163 gc->chip_types->regs.mask = AL_FIC_MASK; in al_fic_register()
164 gc->chip_types->regs.ack = AL_FIC_CAUSE; in al_fic_register()
165 gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit; in al_fic_register()
166 gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit; in al_fic_register()
167 gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit; in al_fic_register()
168 gc->chip_types->chip.irq_set_type = al_fic_irq_set_type; in al_fic_register()
169 gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger; in al_fic_register()
170 gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE; in al_fic_register()
H A Dirq-digicolor.c64 gc->chip_types[0].regs.ack = ack_reg; in digicolor_set_gc()
65 gc->chip_types[0].regs.mask = en_reg; in digicolor_set_gc()
66 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in digicolor_set_gc()
67 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in digicolor_set_gc()
68 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in digicolor_set_gc()
H A Dirq-nvic.c116 gc->chip_types[0].regs.enable = NVIC_ISER; in nvic_of_init()
117 gc->chip_types[0].regs.disable = NVIC_ICER; in nvic_of_init()
118 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in nvic_of_init()
119 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in nvic_of_init()
123 gc->chip_types[0].chip.irq_eoi = irq_gc_noop; in nvic_of_init()
H A Dirq-renesas-irqc.c189 p->gc->chip_types[0].regs.enable = IRQC_EN_SET; in irqc_probe()
190 p->gc->chip_types[0].regs.disable = IRQC_EN_STS; in irqc_probe()
191 p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in irqc_probe()
192 p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in irqc_probe()
193 p->gc->chip_types[0].chip.irq_set_type = irqc_irq_set_type; in irqc_probe()
194 p->gc->chip_types[0].chip.irq_set_wake = irqc_irq_set_wake; in irqc_probe()
195 p->gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND; in irqc_probe()
H A Dirq-atmel-aic5.c350 gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR; in aic5_of_init()
351 gc->chip_types[0].chip.irq_mask = aic5_mask; in aic5_of_init()
352 gc->chip_types[0].chip.irq_unmask = aic5_unmask; in aic5_of_init()
353 gc->chip_types[0].chip.irq_retrigger = aic5_retrigger; in aic5_of_init()
354 gc->chip_types[0].chip.irq_set_type = aic5_set_type; in aic5_of_init()
355 gc->chip_types[0].chip.irq_suspend = aic5_suspend; in aic5_of_init()
356 gc->chip_types[0].chip.irq_resume = aic5_resume; in aic5_of_init()
357 gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown; in aic5_of_init()
H A Dirq-dw-apb-ictl.c194 gc->chip_types[0].regs.mask = APB_INT_MASK_L; in dw_apb_ictl_init()
195 gc->chip_types[0].regs.enable = APB_INT_ENABLE_L; in dw_apb_ictl_init()
196 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in dw_apb_ictl_init()
197 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; in dw_apb_ictl_init()
198 gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; in dw_apb_ictl_init()
H A Dirq-stm32-exti.c374 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; in stm32_exti_init()
375 gc->chip_types->chip.irq_ack = stm32_irq_ack; in stm32_exti_init()
376 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; in stm32_exti_init()
377 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; in stm32_exti_init()
378 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; in stm32_exti_init()
379 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; in stm32_exti_init()
384 gc->chip_types->regs.mask = stm32_bank->imr_ofst; in stm32_exti_init()
H A Dirq-atmel-aic-common.c251 gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK; in aic_common_of_init()
252 gc->chip_types[0].chip.irq_eoi = irq_gc_eoi; in aic_common_of_init()
253 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; in aic_common_of_init()
254 gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown; in aic_common_of_init()
H A Dirq-csky-apb-intc.c67 gc->chip_types[0].regs.mask = mask_reg; in ck_set_gc()
68 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in ck_set_gc()
69 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in ck_set_gc()
72 gc->chip_types[0].chip.irq_unmask = irq_ck_mask_set_bit; in ck_set_gc()
H A Dirq-bcm7120-l2.c87 struct irq_chip_type *ct = gc->chip_types; in bcm7120_l2_intc_suspend()
98 struct irq_chip_type *ct = gc->chip_types; in bcm7120_l2_intc_resume()
295 ct = gc->chip_types; in bcm7120_l2_intc_probe()
/linux/drivers/gpio/
H A Dgpio-tb10x.c202 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH; in tb10x_gpio_probe()
203 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in tb10x_gpio_probe()
204 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in tb10x_gpio_probe()
205 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in tb10x_gpio_probe()
206 gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type; in tb10x_gpio_probe()
207 gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE; in tb10x_gpio_probe()
208 gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN; in tb10x_gpio_probe()
H A Dgpio-rockchip.c544 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; in rockchip_interrupts_register()
545 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; in rockchip_interrupts_register()
546 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in rockchip_interrupts_register()
547 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in rockchip_interrupts_register()
548 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; in rockchip_interrupts_register()
549 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; in rockchip_interrupts_register()
550 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; in rockchip_interrupts_register()
551 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; in rockchip_interrupts_register()
552 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; in rockchip_interrupts_register()
553 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; in rockchip_interrupts_register()
[all …]
/linux/kernel/irq/
H A Dgeneric-chip.c222 struct irq_chip_type *ct = gc->chip_types; in irq_init_generic_chip()
231 gc->chip_types->handler = handler; in irq_init_generic_chip()
251 gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL); in irq_alloc_generic_chip()
263 struct irq_chip_type *ct = gc->chip_types; in irq_gc_init_mask_cache()
306 gc_sz = struct_size(gc, chip_types, info->num_ct); in irq_domain_alloc_generic_chips()
476 ct = gc->chip_types; in irq_map_generic_chip()
546 struct irq_chip_type *ct = gc->chip_types; in irq_setup_generic_chip()
590 struct irq_chip_type *ct = gc->chip_types; in irq_setup_alt_chip()
672 struct irq_chip_type *ct = gc->chip_types; in irq_gc_suspend()
692 struct irq_chip_type *ct = gc->chip_types; in irq_gc_resume()
[all …]
/linux/arch/arm/mach-imx/
H A Davic.c85 struct irq_chip_type *ct = gc->chip_types; in avic_irq_suspend()
107 struct irq_chip_type *ct = gc->chip_types; in avic_irq_resume()
135 ct = gc->chip_types; in avic_init_gc()
/linux/arch/arm/plat-orion/
H A Dirq.c34 ct = gc->chip_types; in orion_irq_init()
/linux/drivers/soc/dove/
H A Dpmu.c296 gc->chip_types[0].regs.mask = PMC_IRQ_MASK; in dove_init_pmu_irq()
297 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in dove_init_pmu_irq()
298 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in dove_init_pmu_irq()

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