| /linux/drivers/clk/ |
| H A D | clk-versaclock7.c | 886 clk_hw_get_name(hw)); in vc7_fod_recalc_rate()
896 __func__, clk_hw_get_name(hw), in vc7_fod_recalc_rate()
917 __func__, clk_hw_get_name(hw), in vc7_fod_round_rate()
931 __func__, clk_hw_get_name(hw), rate, parent_rate); in vc7_fod_set_rate()
936 rate, clk_hw_get_name(hw)); in vc7_fod_set_rate()
946 __func__, clk_hw_get_name(hw), in vc7_fod_set_rate()
969 clk_hw_get_name(hw)); in vc7_iod_recalc_rate()
1010 rate, clk_hw_get_name(hw)); in vc7_iod_set_rate()
1041 clk_hw_get_name(hw)); in vc7_clk_out_prepare()
1061 clk_hw_get_name(hw)); in vc7_clk_out_unprepare()
[all …]
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| H A D | clk-xgene.c | 64 pr_debug("%s pll %s\n", clk_hw_get_name(hw), in xgene_clk_pll_is_enabled()
112 clk_hw_get_name(hw), fvco / nout, parent_rate, in xgene_clk_pll_recalc_rate()
453 pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); in xgene_clk_enable()
461 clk_hw_get_name(hw), in xgene_clk_enable()
472 clk_hw_get_name(hw), in xgene_clk_enable()
493 pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); in xgene_clk_disable()
519 pr_debug("%s clock checking\n", clk_hw_get_name(hw)); in xgene_clk_is_enabled()
522 pr_debug("%s clock is %s\n", clk_hw_get_name(hw), in xgene_clk_is_enabled()
545 clk_hw_get_name(hw), in xgene_clk_recalc_rate()
551 clk_hw_get_name(hw), parent_rate, parent_rate); in xgene_clk_recalc_rate()
[all …]
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| H A D | clk-versaclock5.c | 1059 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1079 parent_names[0] = clk_hw_get_name(&vc5->clk_mul); in vc5_probe()
1081 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1099 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd); in vc5_probe()
1122 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); in vc5_probe()
1144 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1157 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw); in vc5_probe()
1159 parent_names[1] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1162 clk_hw_get_name(&vc5->clk_out[n - 1].hw); in vc5_probe()
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| H A D | clk-fixed-rate_test.c | 188 KUNIT_ASSERT_STREQ(test, parent_name, clk_hw_get_name(parent_hw)); in clk_fixed_rate_parent_test()
221 KUNIT_ASSERT_STREQ(test, parent_name, clk_hw_get_name(parent_hw)); in clk_fixed_rate_parent_rate_test()
251 KUNIT_ASSERT_STREQ(test, parent_name, clk_hw_get_name(parent_hw)); in clk_fixed_rate_parent_accuracy_test()
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| H A D | clk-si5351.c | 438 __func__, clk_hw_get_name(hw), in si5351_pll_recalc_rate()
497 __func__, clk_hw_get_name(hw), a, b, c, in si5351_pll_determine_rate()
530 __func__, clk_hw_get_name(hw), in si5351_pll_set_rate()
641 __func__, clk_hw_get_name(hw), in si5351_msynth_recalc_rate()
755 __func__, clk_hw_get_name(hw), a, b, c, divby4, in si5351_msynth_determine_rate()
789 __func__, clk_hw_get_name(hw), in si5351_msynth_set_rate()
932 __func__, clk_hw_get_name(&drvdata->clkout[num].hw), in _si5351_clkout_reset_pll()
1091 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_determine_rate()
1143 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_set_rate()
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| /linux/drivers/clk/ti/ |
| H A D | clockdomain.c | 43 clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
49 __func__, clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
55 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); in omap2_clkops_enable_clkdm()
77 clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
83 __func__, clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
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| H A D | clkt_dflt.c | 106 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready()
213 __func__, clk_hw_get_name(hw), in omap2_dflt_clk_enable()
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| H A D | dpll3xxx.c | 69 clk_name = clk_hw_get_name(&clk->hw); in _omap3_wait_dpll_status()
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
193 clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_bypass()
223 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_stop()
538 __func__, clk_hw_get_name(hw), in omap3_noncore_dpll_enable()
675 clk_hw_get_name(hw), rate); in omap3_noncore_dpll_set_rate()
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| /linux/drivers/clk/ux500/ |
| H A D | clk-prcmu.c | 46 clk_hw_get_name(hw)); in clk_prcmu_unprepare()
77 (char *)clk_hw_get_name(hw), in clk_prcmu_opp_prepare()
81 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
90 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
104 clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
110 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
124 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_volt_prepare()
146 clk_hw_get_name(hw)); in clk_prcmu_opp_volt_unprepare()
314 clk_hw_get_name(hw)); in clk_prcmu_clkout_unprepare()
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| /linux/drivers/clk/zynqmp/ |
| H A D | pll.c | 53 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode()
138 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_recalc_rate()
182 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_rate()
228 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_is_enabled()
252 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_enable()
280 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_disable()
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| H A D | clk-gate-zynqmp.c | 37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled()
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| H A D | clk-mux-zynqmp.c | 46 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_get_parent()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_set_parent()
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| H A D | divider.c | 83 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_recalc_rate()
126 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_round_rate()
173 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_set_rate()
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_frac.c | 71 pr_debug("%s: Read fractional\n", clk_hw_get_name(&common->hw)); in ccu_frac_helper_read_rate()
77 clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]); in ccu_frac_helper_read_rate()
82 clk_hw_get_name(&common->hw), reg, cf->select); in ccu_frac_helper_read_rate()
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| H A D | ccu_sdm.c | 118 clk_hw_get_name(&common->hw)); in ccu_sdm_helper_read_rate()
124 clk_hw_get_name(&common->hw)); in ccu_sdm_helper_read_rate()
129 clk_hw_get_name(&common->hw), reg); in ccu_sdm_helper_read_rate()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-regmap-mux-div.c | 27 const char *name = clk_hw_get_name(&md->clkr.hw); in mux_div_set_src_div()
63 const char *name = clk_hw_get_name(&md->clkr.hw); in mux_div_get_src_div()
166 const char *name = clk_hw_get_name(hw); in mux_div_get_parent()
208 const char *name = clk_hw_get_name(hw); in mux_div_recalc_rate()
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| H A D | clk-branch.c | 66 const char *name = clk_hw_get_name(&br->clkr.hw); in clk_branch_wait()
151 WARN(1, "%s mem enable failed\n", clk_hw_get_name(&branch.clkr.hw)); in clk_branch2_mem_enable()
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| /linux/drivers/clk/st/ |
| H A D | clkgen-fsyn.c | 342 clk_hw_get_name(hw), __func__); in quadfs_pll_fs660c32_recalc_rate()
390 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_round_rate()
415 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_set_rate()
573 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_enable()
598 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_disable()
615 __func__, clk_hw_get_name(hw), nsb); in quadfs_fsynth_is_enabled()
809 clk_hw_get_name(hw), __func__); in quadfs_recalc_rate()
812 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in quadfs_recalc_rate()
825 __func__, clk_hw_get_name(hw), in quadfs_round_rate()
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| /linux/drivers/clk/berlin/ |
| H A D | berlin2-pll.c | 53 pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw)); in berlin2_pll_recalc_rate()
62 clk_hw_get_name(hw), vcodivsel); in berlin2_pll_recalc_rate()
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| /linux/drivers/clk/imx/ |
| H A D | clk-scu.c | 248 clk_hw_get_name(hw), ret); in clk_scu_recalc_rate()
357 clk_hw_get_name(hw), ret); in clk_scu_get_parent()
385 clk_hw_get_name(hw), ret); in clk_scu_set_parent()
441 pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), in clk_scu_unprepare()
602 dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent), in imx_clk_scu_suspend()
627 clk_hw_get_name(clk->parent), in imx_clk_scu_resume()
841 pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), in clk_gpr_gate_scu_unprepare()
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| H A D | clk-pll14xx.c | 153 clk_hw_get_name(&pll->hw), prate, rate); in imx_pll14xx_calc_settings()
175 clk_hw_get_name(&pll->hw), prate, rate, in imx_pll14xx_calc_settings()
213 clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv, in imx_pll14xx_calc_settings()
295 clk_hw_get_name(hw)); in clk_pll1416x_set_rate()
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-sg2042-pll.c | 345 clk_hw_get_name(hw), rate); in sg2042_clk_pll_recalc_rate()
369 clk_hw_get_name(hw), proper_rate); in sg2042_clk_pll_round_rate()
379 clk_hw_get_name(hw), req->rate); in sg2042_clk_pll_determine_rate()
414 clk_hw_get_name(hw), value); in sg2042_clk_pll_set_rate()
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| /linux/drivers/clk/samsung/ |
| H A D | clk-pll.c | 111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
259 drate, clk_hw_get_name(hw)); in samsung_pll35xx_set_rate()
368 drate, clk_hw_get_name(hw)); in samsung_pll36xx_set_rate()
476 drate, clk_hw_get_name(hw)); in samsung_pll0822x_set_rate()
565 drate, clk_hw_get_name(hw)); in samsung_pll0831x_set_rate()
675 drate, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
812 drate, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
1050 drate, clk_hw_get_name(hw)); in samsung_pll2550xx_set_rate()
1145 drate, clk_hw_get_name(hw)); in samsung_pll2650x_set_rate()
1235 drate, clk_hw_get_name(hw)); in samsung_pll2650xx_set_rate()
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| /linux/drivers/clk/socfpga/ |
| H A D | clk-gate.c | 33 const char *name = clk_hw_get_name(hwclk); in socfpga_clk_get_parent()
59 const char *name = clk_hw_get_name(hwclk); in socfpga_clk_set_parent()
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| H A D | clk-gate-s10.c | 56 const char *name = clk_hw_get_name(hwclk); in socfpga_gate_get_parent()
86 const char *name = clk_hw_get_name(hwclk); in socfpga_agilex_gate_get_parent()
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